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1. 发明授权

US06774395B1 Apparatus and methods for characterizing floating body effects in SOI devices 失效
标题翻译：用于表征SOI器件中浮体效应的装置和方法
公开(公告)号：US06774395B1
公开(公告)日：2004-08-10
申请号：US10345007
申请日：2003-01-15
申请人： Hung-Jen Lin , W Eugene Hill , Mario M. Pelella , Chern-Jann Lee , Srikanth Sundararajan , Siu May Ho
发明人： Hung-Jen Lin , W Eugene Hill , Mario M. Pelella , Chern-Jann Lee , Srikanth Sundararajan , Siu May Ho
IPC分类号： H01L2358
CPC分类号： H01L22/34
摘要： Methods are described for characterizing floating body delay effects in SOI wafers comprising providing a pulse edge to a floating body and a tied body chain in the wafer, storing tied body chain data according to one or more of the floating body devices, and characterizing the floating body delay effects according to the stored tied body chain data. Test apparatus are also described comprising a floating body chain including a plurality of series connected floating body inverters or NAND gates fabricated in the wafer and a tied body chain comprising a plurality of series connected tied body devices to in the wafer. Storage devices are coupled with the tied body devices and with one or more of the floating body devices and operate to store tied body chain data from the tied body devices according to one or more signals from floating body chain.
摘要翻译：描述了用于表征SOI晶片中的浮体延迟效应的方法，包括向晶片中的浮体和绑定的主体链提供脉冲边缘，根据一个或多个浮体装置存储绑定的身体链数据，并表征浮动根据存储的绑定的身体链数据的身体延迟效应。还描述了测试装置，其包括浮体体链，其包括在晶片中制造的多个串联连接的浮体反相器或NAND门，以及包括多个串联连接的绑定体装置的晶片的绑定体链。存储装置与绑定的身体装置和一个或多个浮体装置相耦合，并根据来自浮体的一个或多个信号，操作以从捆绑的身体装置中存储绑定的身体链数据。

2. 发明授权

US08725748B1 Method and system for storing and retrieving semiconductor tester information 有权
标题翻译：存储和检索半导体测试仪信息的方法和系统
公开(公告)号：US08725748B1
公开(公告)日：2014-05-13
申请号：US10929038
申请日：2004-08-27
申请人： Srikanth Sundararajan , Siu May Ho , Shivananda S. Shetty
发明人： Srikanth Sundararajan , Siu May Ho , Shivananda S. Shetty
IPC分类号： G06F17/30
CPC分类号： G01R31/318314
摘要： A tester information tester information processing system provides test equipment for generating test data. A markup language encoder connected to the test equipment encodes the test data for storage in an object-oriented database management system connected to the markup language encoder, and a user interface is operatively connected to the object-oriented database management system for retrieval of the test data.
摘要翻译：测试仪信息测试仪信息处理系统提供测试设备生成测试数据。连接到测试设备的标记语言编码器对连接到标记语言编码器的面向对象的数据库管理系统中存储的测试数据进行编码，并且用户界面可操作地连接到面向对象的数据库管理系统以检索测试数据。

3. 发明授权

US07634127B1 Efficient storage of fail data to aid in fault isolation 失效
标题翻译：故障数据的有效存储有助于故障隔离
公开(公告)号：US07634127B1
公开(公告)日：2009-12-15
申请号：US10884333
申请日：2004-07-01
申请人： Srikanth Sundararajan , Siu May Ho , Shivananda S. Shetty
发明人： Srikanth Sundararajan , Siu May Ho , Shivananda S. Shetty
IPC分类号： G06K9/00 , G01R31/26
CPC分类号： G01R31/318511 , G01R31/2894 , G06T11/206
摘要： A method and system for fault isolation in semiconductor with devices thereon includes determining test data from a plurality of semiconductor devices and creating a failure bitmap of locations of the plurality of semiconductor devices and test data in a vector graphic CAD format. The vector graphic CAD format allows storage of test data on multiple layers.
摘要翻译：一种用于其中装置的半导体中的故障隔离的方法和系统，包括：确定来自多个半导体器件的测试数据，并以向量图形CAD格式创建多个半导体器件的位置以及测试数据的故障位图。矢量图形CAD格式允许在多层存储测试数据。

4. 发明授权

US06700430B1 Method to reduce time to dynamic steady-state condition 失效
标题翻译：减少时间到动态稳态条件的方法
公开(公告)号：US06700430B1
公开(公告)日：2004-03-02
申请号：US10188173
申请日：2002-08-20
申请人： Mario M. Pelella , Srikanth Sundararajan
发明人： Mario M. Pelella , Srikanth Sundararajan
IPC分类号： H03K1704
CPC分类号： H01L27/1203 , H01L29/78612 , H03K3/012
摘要： A method for reducing the time for a partially depleted/silicon-on-insulator (PD/SOI) based circuit to reach a dynamic steady state pre-conditions the PD/SOI-based circuit by initially charging the circuit at a voltage greater than the normal operating voltage. The circuit is then charged at the normal operating voltage after a predetermined amount of time. By pre-conditioning the circuit in this manner, the amount of time required for the PD/SOI transistors of the circuit to reach their dynamic steady state (DSS) condition is shortened.
摘要翻译：一种减少部分耗尽/绝缘体上（基于硅）的电路达到动态稳态的时间的方法通过以大于该电压的电压对电路进行初始充电来预先调节基于PD / SOI的电路正常工作电压。然后在预定时间量之后，在正常工作电压下对电路进行充电。通过以这种方式对电路进行预调节，电路的PD / SOI晶体管达到其动态稳态（DSS）条件所需的时间被缩短。

5. 发明授权

US07137085B1 Wafer level global bitmap characterization in integrated circuit technology development 有权
标题翻译：晶圆级全局位图表征在集成电路技术开发中
公开(公告)号：US07137085B1
公开(公告)日：2006-11-14
申请号：US10858739
申请日：2004-06-01
申请人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
发明人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/31718 , G01R31/318511
摘要： A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.
摘要翻译：用于晶片级全局位图表征的系统和方法包括从半导体晶片确定芯片级缺陷数据位图，以及将芯片级缺陷数据位图合并到表征基本上整个晶片故障配置的全局晶片级位图中。然后分析全球晶圆级位图并与其他全球晶圆级位图进行比较，以开发相关性，并开发全球晶圆级位图定义，用于进行晶圆到晶片，船对船和批次位图中的至少一个，基于全球晶圆级位图定义的批量处理分析。

6. 发明授权

US09082735B1 3-D silicon on glass based organic light emitting diode display 有权
标题翻译： 3-D硅玻璃基有机发光二极管显示屏
公开(公告)号：US09082735B1
公开(公告)日：2015-07-14
申请号：US14522883
申请日：2014-10-24
申请人： Srikanth Sundararajan
发明人： Srikanth Sundararajan
IPC分类号： H01L29/08 , H01L51/00 , H01L27/32 , H01L51/52 , H01L49/02 , H01L29/786 , H01L29/792 , H01L29/78
CPC分类号： H01L51/5287 , H01L27/1214 , H01L27/3209 , H01L27/3246 , H01L27/3248 , H01L27/3251 , H01L27/3258 , H01L27/326 , H01L51/504 , H01L51/5209 , H01L51/5225 , H01L51/5278
摘要： An organic light emitting display includes an organic light emitting diode that further includes an anode metal connected to a transparent cathode. An organic diode stack further comprising: electron-transport layer, hole transport layer and the emission layer organized into deep trench high aspect ratio structures in a bottom plane of the organic light emitting display and sandwiched between and the anode and cathode layers described above. A first stratum of thin transparent silicon that is attached to a diode plane in the organic light emitting display through a high aspect ratio via. A second stratum of thin transparent silicon that is attached to the first stratum and forming addressing transistors for the devices on the first strata. The organic light emitting diode emits light in response to bias voltages existing on the first and second strata that is extracted through a sub-pixel pitch microlens film deposited on the glass substrate.
摘要翻译：有机发光显示器包括还包括连接到透明阴极的阳极金属的有机发光二极管。一种有机二极管堆叠，其还包括：电子传输层，空穴传输层和在有机发光显示器的底部平面中组织成深沟槽高纵横比结构的发射层，并夹在上述阳极和阴极层之间。薄的透明硅的第一层，通过高纵横比通孔连接到有机发光显示器中的二极管平面。薄的透明硅的第二层，其连接到第一层，并形成用于第一层上的器件的寻址晶体管。有机发光二极管响应于通过沉积在玻璃基板上的子像素间距微透镜膜提取的第一和第二层上存在的偏压而发光。

7. 发明授权

US5412758A Flexible system for knowledge acquisition in expert system development 失效
标题翻译：灵活的知识获取系统专家系统开发
公开(公告)号：US5412758A
公开(公告)日：1995-05-02
申请号：US965985
申请日：1992-10-23
申请人： Usha Srikanth , Srikanth Sundararajan
发明人： Usha Srikanth , Srikanth Sundararajan
IPC分类号： G06N5/02 , G06F15/18
CPC分类号： G06N5/022
摘要： An interface to an artificial intelligence system shell is provided to facilitate the task of knowledge acquisition, knowledge refinement, knowledgebase addition/modification, knowledgebase maintenance and information management relating to a specific expert system project. The interface communicates with an artificial intelligence system via a Unix.RTM. pipe to pass knowledge data therebetween in accordance with high level functions selected by the user. Preferably, these high level functions are selected via a user friendly interface such as windows. The present invention thus allows the artificial intelligence system shell to be used by those who are not particularly familiar with the artificial intelligence program by allowing the user to communicate with the artificial intelligence program without understanding the details of the artificial intelligence programming language. Since the expert system shell is accessible by a wider variety of users, the knowledgebase can be updated more efficiently such that the real benefits of artificial intelligence can be appreciated. Also, the invention may be used in a manufacturing environment along with a video interface to allow real-time analysis and control of production defects.
摘要翻译：提供人工智能系统外壳的接口，以便于与特定专家系统项目相关的知识获取，知识改进，知识库添加/修改，知识库维护和信息管理等任务。接口通过Unix TM管道与人造智能系统通信，以根据用户选择的高级功能在其间传递知识数据。优选地，这些高级功能通过诸如Windows的用户友好的界面来选择。因此，本发明允许人造智能系统壳由不熟悉人造智能程序的人使用，允许用户在不理解人工智能编程语言的细节的情况下与人工智能程序进行通信。由于专家系统shell可以被更多种类的用户访问，因此可以更有效地更新知识库，从而可以欣赏人造智能的真正好处。此外，本发明可以与制造环境一起用于视频接口，以允许对生产缺陷的实时分析和控制。

8. 发明授权

US07888771B1 E-fuse with scalable filament link 有权
标题翻译：电源保险丝与可伸缩灯丝连接
公开(公告)号：US07888771B1
公开(公告)日：2011-02-15
申请号：US11799886
申请日：2007-05-02
申请人： Lakhbeer Singh Sidhu , Srikanth Sundararajan , Michael J. Hart
发明人： Lakhbeer Singh Sidhu , Srikanth Sundararajan , Michael J. Hart
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10S257/904 , H01L2924/00
摘要： An electronic fuse (“E-fuse”) has a silicide filament link extending along a gap between polysilicon structures formed on a silicon substrate. The silicide filament link extends across diffusions formed in the gap. A P-N junction between terminals of the E-fuse provides high resistivity after programming (fusing) the silicide filament link.
摘要翻译：电子熔丝（“E熔丝”）具有沿着形成在硅衬底上的多晶硅结构之间的间隙延伸的硅化物细丝连接。硅化物长丝连接延伸穿过在间隙中形成的扩散。电熔丝端子之间的P-N结，在对硅化物丝线连接进行编程（熔化）之后提供高电阻率。

9. 发明授权

US07529988B1 Storage of descriptive information in user defined fields of failure bitmaps in integrated circuit technology development 失效
标题翻译：在用户定义的故障位图字段中将描述信息存储在集成电路技术开发中
公开(公告)号：US07529988B1
公开(公告)日：2009-05-05
申请号：US10654247
申请日：2003-09-02
申请人： Srikanth Sundararajan
发明人： Srikanth Sundararajan
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/56 , G01R31/31718 , G11C29/56008 , G11C2029/5604
摘要： A system for processing tester information including receiving data from a tester and forming a user defined field for storing descriptive information. A bitmap is created and compressed into a compressed image. The user defined field and the compressed image are then combined into a data structure.
摘要翻译：一种用于处理测试器信息的系统，包括从测试器接收数据并形成用于存储描述信息的用户定义字段。创建位图并将其压缩成压缩图像。然后将用户定义的字段和压缩的图像组合成数据结构。

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