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1. 发明授权

US07137085B1 Wafer level global bitmap characterization in integrated circuit technology development 有权
标题翻译：晶圆级全局位图表征在集成电路技术开发中
公开(公告)号：US07137085B1
公开(公告)日：2006-11-14
申请号：US10858739
申请日：2004-06-01
申请人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
发明人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/31718 , G01R31/318511
摘要： A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.
摘要翻译：用于晶片级全局位图表征的系统和方法包括从半导体晶片确定芯片级缺陷数据位图，以及将芯片级缺陷数据位图合并到表征基本上整个晶片故障配置的全局晶片级位图中。然后分析全球晶圆级位图并与其他全球晶圆级位图进行比较，以开发相关性，并开发全球晶圆级位图定义，用于进行晶圆到晶片，船对船和批次位图中的至少一个，基于全球晶圆级位图定义的批量处理分析。

2. 发明授权

US06524916B1 Controlled gate length and gate profile semiconductor device and manufacturing method therefor 有权
标题翻译：控制栅极长度和栅极配置半导体器件及其制造方法
公开(公告)号：US06524916B1
公开(公告)日：2003-02-25
申请号：US10137568
申请日：2002-05-01
申请人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
发明人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer that are a function of the thickness of the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.
摘要翻译：提供了一种超大规模集成电路半导体器件，其具有具有逐渐掺杂分布的LDD结构的倒梯形栅极并且用于接触。通过在衬底上形成阻挡层，在阻挡层上形成栅极层，在栅极层中形成倒梯形栅极沟槽，栅极层的厚度为栅极层的厚度，沉积栅极电介质在衬底上的倒梯形栅极沟槽中，在反向梯形栅极沟槽中形成多晶硅栅极，去除栅极层和势垒层以限定栅极间隔物，用掺杂剂将栅极间隔物周围注入基板以形成源极/漏极延伸结并且准备用于导电连接的源极/漏极延伸结和栅极。

3. 发明授权

US06512842B1 Composition based association engine for image archival systems 失效
标题翻译：用于图像存档系统的基于组合的关联引擎
公开(公告)号：US06512842B1
公开(公告)日：2003-01-28
申请号：US09288938
申请日：1999-04-09
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06K900
CPC分类号： G06K9/033 , G06K2209/19 , G06T7/0006 , G06T2207/10061 , G06T2207/30148
摘要： A method of analyzing defect images in a semiconductor manufacturing process wherein descriptors are assigned to images of defects caught during scanning of an inspection wafer. The images, assigned descriptors and linkage data are stored in a relational database. An operator can select an image to analyze and the review station assigns descriptors to the selected image and the database is searched for images having the assigned descriptors.
摘要翻译：一种在半导体制造过程中分析缺陷图像的方法，其中描述符被分配给在检查晶片的扫描期间捕获的缺陷的图像。图像，分配的描述符和链接数据存储在关系数据库中。操作员可以选择要分析的图像，并且审查站将所描述的图像分配给所选择的图像，并且搜索具有分配的描述符的图像的数据库。

4. 发明授权

US06506639B1 Method of forming low resistance reduced channel length transistors 有权
标题翻译：形成低电阻减少沟道长度晶体管的方法
公开(公告)号：US06506639B1
公开(公告)日：2003-01-14
申请号：US09691717
申请日：2000-10-18
申请人： Allen S. Yu , Paul J. Steffan
发明人： Allen S. Yu , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/823807 , H01L21/823828 , H01L29/66553
摘要： Methods of manufacturing semiconductor devices having low resistance reduced channel length transistors. Spacers are formed on each side of trenches that define the location of transistor channels. The spacers are formed with a dimension between the spacers that is less than a dimension available from photolithography systems currently available. A layer of gate oxide and a polysilicon gate are formed within the dimension resulting in transistors having channels length less than that available from standard photolithographic methods of forming gates and channels.
摘要翻译：制造具有低阻抗的沟道长度晶体管的半导体器件的方法。在沟槽的每一侧上形成间隔物，其限定晶体管通道的位置。间隔件形成在间隔件之间的尺寸小于可用于目前可获得的光刻系统的尺寸。在该尺寸内形成栅极氧化物层和多晶硅栅极，导致晶体管的沟道长度小于从形成栅极和沟道的标准光刻方法获得的沟道长度。

5. 发明授权

US06468815B1 Overlay radius offset shift engine 失效
标题翻译：叠加半径偏移换档引擎
公开(公告)号：US06468815B1
公开(公告)日：2002-10-22
申请号：US09476582
申请日：2000-01-03
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： H01L2166
CPC分类号： H01L22/20
摘要： A method of reducing the effect of placement errors during defect capture and analysis during the manufacture of integrated devices on semiconductor wafers wherein defects from a current layer are evaluated in relation to defects from previous layers after an oversized overlay map has been utilized to perform a best-fit analysis of current defects and previous defects, the oversized overlay map reduced and a trend analysis performed to determine error type and the coordinates of defects translated to their proper location.
摘要翻译：一种降低在半导体晶片上集成器件制造期间的缺陷捕获和分析期间放置误差的影响的方法，其中来自当前层的缺陷相对于来自先前层的缺陷被评估，在超大重叠贴图被用于执行最佳对当前缺陷和以前的缺陷进行了分析，减小了超大的覆盖图，并进行了一个趋势分析，以确定错误类型和缺陷的坐标转换为正确的位置。

6. 发明授权

US06463171B1 Automatic defect resizing tool 有权
标题翻译：自动缺陷调整工具
公开(公告)号：US06463171B1
公开(公告)日：2002-10-08
申请号：US09345174
申请日：1999-06-30
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06K900
CPC分类号： G06T7/0004 , G01N21/9501 , G01N2021/8854 , G01N2021/8861 , G06T2207/30148 , H01L21/67288 , H01L22/20
摘要： A method of analyzing and classifying defects on a semiconductor wafer during a semiconductor manufacturing process using an automatic defect resizing tool to accurately measure the sizes of defects.
摘要翻译：在使用自动缺陷调整工具的半导体制造过程中对半导体晶片上的缺陷进行分析和分类的方法，以精确地测量缺陷的尺寸。

7. 发明授权

US06303394B1 Global cluster pre-classification methodology 失效
标题翻译：全球集群预分类方法
公开(公告)号：US06303394B1
公开(公告)日：2001-10-16
申请号：US09186052
申请日：1998-11-03
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G01R3126
CPC分类号： H01L22/20
摘要： A method of detecting and pre-classifying cluster type defects in a process for manufacturing semiconductor wafers. At least one inspection wafer is selected from a set of semiconductor wafers being process and the first layer of the set is processed. The first layer is scanned for defect information and it is determined whether a cluster pattern exists and comparing the cluster pattern to patterns stored in a pattern detection and classification register and pre-classifying the cluster pattern if a cluster pattern is detected and updating a defect database with comparison and pre-classification information for the first layer. Repeating the process for the next layer.
摘要翻译：在制造半导体晶片的工艺中检测和预分类型缺陷的方法。从正在处理的一组半导体晶片中选择至少一个检查晶片，并且处理该组的第一层。扫描第一层的缺陷信息，确定是否存在集群模式，并将集群模式与存储在模式检测和分类寄存器中的模式进行比较，并且如果检测到集群模式并对其进行预分类，并更新缺陷数据库与第一层的比较和预分类信息。重复下一层的过程。

8. 发明授权

US06287968B1 Method of defining copper seed layer for selective electroless plating processing 有权
标题翻译：定义用于选择性化学镀处理的铜籽晶层的方法
公开(公告)号：US06287968B1
公开(公告)日：2001-09-11
申请号：US09225175
申请日：1999-01-04
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76879
摘要： A method of manufacturing semiconductor wafers using electroless plating processing. A partially completed semiconductor wafer having trenches and vias formed in a layer of interlayer dielectric has a barrier layer globally formed on the surface of the partially completed semiconductor wafer. A seed layer is globally formed on the surface of the barrier layer. The barrier and seed layers are removed from portions of the surface of the partially completed semiconductor wafer on which plating is not to occur. The partially completed semiconductor wafer is then subjected to an electroless plating process and conductive material is plated on those portions of the seed layer that remains on the partially completed semiconductor wafer.
摘要翻译：使用化学镀处理制造半导体晶片的方法。在层间电介质层中形成的具有沟槽和通孔的部分完成的半导体晶片具有全部形成在部分完成的半导体晶片的表面上的势垒层。种子层全局地形成在阻挡层的表面上。从不发生电镀的部分完成的半导体晶片的表面的部分去除阻挡层和种子层。然后对部分完成的半导体晶片进行化学镀处理，并且将导电材料电镀在保留在部分完成的半导体晶片上的籽晶层的那些部分上。

9. 发明授权

US06185511B2 Method to accurately determine classification codes for defects during semiconductor manufacturing 失效
标题翻译：准确地确定半导体制造过程中的缺陷分类代码的方法
公开(公告)号：US06185511B2
公开(公告)日：2001-02-06
申请号：US08979629
申请日：1997-11-28
申请人： Paul J. Steffan , Ming Chun Chen
发明人： Paul J. Steffan , Ming Chun Chen
IPC分类号： G06F1900
CPC分类号： G06K9/00 , G06T7/0004 , G06T2207/30148 , H01L22/20
摘要： A method of determining classification codes for defects occurring in semiconductor processes comparing images of defects from a first selected wafer with images of defects in a first image reference library. The images in the first image reference library are updated from a master image reference library. The images in the master image reference library are the best images of defect types. The images in the master image reference library are in a format readable by all review stations utilized to review the images of the defect.
摘要翻译：确定在半导体工艺中发生的缺陷的分类代码的方法，其将来自第一选定晶片的缺陷图像与第一图像参考库中的缺陷图像进行比较。第一图像参考库中的图像从主图像参考库更新。主图像参考库中的图像是缺陷类型的最佳图像。主图像参考库中的图像具有可用于审查缺陷图像的所有检查站的格式。

10. 发明授权

US06177287B1 Simplified inter database communication system 失效
标题翻译：简化的数据库间通信系统
公开(公告)号：US06177287B1
公开(公告)日：2001-01-23
申请号：US09162112
申请日：1998-09-28
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G01R3126
CPC分类号： G01R31/2851 , G01R31/2831
摘要： A method of reviewing classification data and image data for defects detected in a series of semiconductor manufacturing processes. An inspection wafer is selected from a production lot of wafers and is inspected after the completion of each of the series of semiconductor manufacturing processes. The classification data for each defect is sent to a defect management system and an image for selected defects is sent to an image storage system. Identification data is sent to the defect management system and the image storage system. The image storage system sends a cookie to the defect management system allowing the defect management system to identify defects having an image. A operator controlled review station allows an operator to select defects for review that have an image available for review.
摘要翻译：一种用于检查在一系列半导体制造工艺中检测到的缺陷的分类数据和图像数据的方法。从晶片的生产批次中选择检查晶片，并且在每个半导体制造工艺完成之后进行检查。将每个缺陷的分类数据发送到缺陷管理系统，并将用于所选缺陷的图像发送到图像存储系统。识别数据被发送到缺陷管理系统和图像存储系统。图像存储系统向缺陷管理系统发送cookie，允许缺陷管理系统识别具有图像的缺陷。操作员控制的检查站允许操作者选择具有可用于审查的图像的审查缺陷。

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