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1. 发明授权

US09224593B2 Method of manufacturing a semiconductor device having a porous, low-k dielectric layer 有权
标题翻译：制造具有多孔低k电介质层的半导体器件的方法
公开(公告)号：US09224593B2
公开(公告)日：2015-12-29
申请号：US13242031
申请日：2011-09-23
申请人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
发明人： Sang-Hoon Ahn , Kyu-Hee Han , Kyoung-Hee Kim , Gil-Heyun Choi , Byung-Hee Kim , Sang-Don Nam
IPC分类号： H01L21/768 , H01L21/312 , C25D1/08 , H01L21/02 , C23C16/40 , C23C16/56
CPC分类号： H01L21/02203 , C23C16/401 , C23C16/56 , C25D1/08 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/76802 , H01L21/7682 , H01L2221/1047
摘要： The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
摘要翻译：本发明构思提供了多孔，低k电介质材料及其制造和使用方法。在一些实施方案中，通过在基材上形成含致孔剂的介电层，然后从该层除去至少一部分所述致孔剂来制造多孔低k电介质材料。

2. 发明授权

US08026543B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US08026543B2
公开(公告)日：2011-09-27
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L27/108 , H01L47/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.
摘要翻译：相变存储器件具有氧化阻挡层以防止存储器细胞污染或氧化。在一个实施例中，半导体存储器件包括设置在半导体衬底上的成型层，相变材料图案和电绝缘材料的氧化屏障。成型层在其上部具有突出部。可相变材料图案的一部分覆盖模制层的突起，并且相变材料图案的另一部分延伸穿过突出部。氧化屏障的电绝缘材料可以覆盖相变材料图案和/或延伸并且覆盖模制层的突起和设置在突起上的相变材料图案的部分邻接的整个区域。

3. 发明申请

US20100248471A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100248471A1
公开(公告)日：2010-09-30
申请号：US12732907
申请日：2010-03-26
申请人： Sang-Don Nam , Sang-Hoon Ahn , Eunkee Hong
发明人： Sang-Don Nam , Sang-Hoon Ahn , Eunkee Hong
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/3105 , H01L21/31144 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.
摘要翻译：提供一种制造半导体器件的方法，包括在第一和第二互连之间形成包括第一和第二互连的互连结构和绝缘材料，在互连上依次形成具有多个微孔的第一掩模层和第二掩模层结构，将第二掩模层中的多个微孔彼此聚结并在第二掩模层中形成多个第一微孔，在第一掩模层中使用多个第一微孔形成多个第二微孔，并且去除绝缘使用具有多个第二微孔的第一掩模层作为蚀刻掩模的材料，以便在第一和第二互连之间形成气隙。

4. 发明申请

US20070243641A1 Method for forming ferroelectric memory device 有权
标题翻译：形成铁电存储器件的方法
公开(公告)号：US20070243641A1
公开(公告)日：2007-10-18
申请号：US11812141
申请日：2007-06-15
申请人： Yoon-Ho Son , Sang-Don Nam , Suk-Hun Choi
发明人： Yoon-Ho Son , Sang-Don Nam , Suk-Hun Choi
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface is formed. A ferroelectric layer is formed on the lower electrode pattern and the seed layer pattern. An upper electrode overlapping the two lower electrode patterns is formed on the ferroelectric layer.
摘要翻译：提供了铁电存储器件及其形成方法。在覆盖半导体衬底的层间绝缘层上形成至少两个下电极图案。形成填充至少两个下电极图案之间并具有平坦表面的空间的晶种层图案。在下部电极图案和种子层图案上形成铁电体层。在强电介质层上形成与两个下电极图案重叠的上电极。

5. 发明授权

US06952028B2 Ferroelectric memory devices with expanded plate line and methods in fabricating the same 失效
标题翻译：具有扩展板线的铁电存储器件及其制造方法
公开(公告)号：US06952028B2
公开(公告)日：2005-10-04
申请号：US10624327
申请日：2003-07-22
申请人： Kyu-Mann Lee , Sang-Don Nam , Kun-Sang Park
发明人： Kyu-Mann Lee , Sang-Don Nam , Kun-Sang Park
IPC分类号： H01L27/105 , H01L21/768 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L21/76804 , H01L21/76841 , H01L21/76852 , H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory device includes a lower interlayer dielectric on a semiconductor substrate, a plurality of ferroelectric capacitors, and a plate line. The ferroelectric capacitors are on the lower interlayer dielectric. The plate line extends across and electrically connects to surfaces of at least two adjacent ones of the plurality of ferroelectric capacitors.
摘要翻译：铁电存储器件包括在半导体衬底上的下层间电介质，多个铁电电容器和板线。铁电电容器位于下层电介质上。板线延伸并且电连接到多个铁电电容器中的至少两个相邻的铁电电容器的表面。

6. 发明授权

US06380579B1 Capacitor of semiconductor device 失效
标题翻译：半导体器件电容器
公开(公告)号：US06380579B1
公开(公告)日：2002-04-30
申请号：US09547940
申请日：2000-04-11
申请人： Sang-don Nam , Jin-won Kim
发明人： Sang-don Nam , Jin-won Kim
IPC分类号： H01L27108
CPC分类号： H01L28/75 , H01L28/55
摘要： A capacitor of a semiconductor device which uses a high dielectric layer and a method of manufacturing the same are provided. The capacitor includes a storage electrode having at least two conductive patterns which overlap each other and a thermally-stable material layer pattern being positioned between the conductive layer patterns. The storage electrode and the thermally-stable material layer pattern are formed by alternately forming a conductive layer and a thermally-stable material layer, and patterning the conductive layer and the thermally-stable material layer to have predetermined shapes. With the present structure, it is possible to prevent the storage electrode from being transformed or broken during a thermal treatment process for forming a high dielectric layer on the storage electrode or in a subsequent high temperature thermal treatment process.
摘要翻译：提供了使用高介电层的半导体器件的电容器及其制造方法。电容器包括具有彼此重叠的至少两个导电图案的存储电极和位于导电层图案之间的热稳定材料层图案。存储电极和热稳定材料层图案通过交替形成导电层和热稳定材料层而形成，并且将导电层和热稳定材料层图案化以具有预定形状。利用本结构，可以防止在用于在存储电极上形成高电介质层的热处理工艺中或在随后的高温热处理工艺中存储电极变形或破裂。

7. 发明授权

US08404579B2 Methods of forming integrated circuit devices with crack-resistant fuse structures 有权
标题翻译：形成具有抗裂熔断结构的集成电路器件的方法
公开(公告)号：US08404579B2
公开(公告)日：2013-03-26
申请号：US12960150
申请日：2010-12-03
申请人： Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Don Nam , Kyu-Hee Han
发明人： Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Don Nam , Kyu-Hee Han
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.
摘要翻译：在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。在沟槽中形成熔丝。保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

8. 发明申请

US20120083117A1 Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer 有权
标题翻译：形成硬化多孔电介质层的方法和制造具有硬化多孔介电层的半导体器件的方法
公开(公告)号：US20120083117A1
公开(公告)日：2012-04-05
申请号：US13238297
申请日：2011-09-21
申请人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-Heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
发明人： Sang-Hoon Ahn , Byung-Hee Kim , Sang-Don Nam , Kyu-Hee Han , Gil-Heyun Choi , Jang-Hee Lee , Jong-Min Baek , Kyoung-Hee Kim
IPC分类号： H01L21/314 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02337 , H01L21/02348 , H01L21/3105 , H01L21/76829 , H01L2221/1047
摘要： Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
摘要翻译：示例性实施方案涉及形成硬化多孔介电层的方法。该方法可以包括在衬底上形成含有致孔剂的电介质层，使用第一UV固化工艺将电介质层转化为多孔介电层，以从电介质层除去致孔剂，并将多孔电介质层转化成交联的多孔介电层使用第二UV固化方法在多孔介电层中产生交联。

9. 发明申请

US20110071302A1 PROCESS FOR PREPARING INTERMEDIATE COMPOUND FOR SYNTHESIZING AN ANTIULCERANT 审中-公开
标题翻译：制备中间体化合物以合成抗生素的方法
公开(公告)号：US20110071302A1
公开(公告)日：2011-03-24
申请号：US12993086
申请日：2008-11-20
申请人： Dong Yeon Kim , Jun Yeoun Lee , Kwi Hyung Cho , Sung Tae Park , Jung Woo Kim , Doo Hyuk Pyun , Sang Don Nam , Hee Yun Kim
发明人： Dong Yeon Kim , Jun Yeoun Lee , Kwi Hyung Cho , Sung Tae Park , Jung Woo Kim , Doo Hyuk Pyun , Sang Don Nam , Hee Yun Kim
IPC分类号： C07D403/10
CPC分类号： C07D403/04
摘要： The present invention relates a novel method of preparing an intermediate which is useful for synthesizing an antiulcerant. The present invention provides a method of preparing an intermediate of an antiulcerant which can obtain a high purity compound in high yield, with reduced production cost/time as compared to a conventional method.
摘要翻译：本发明涉及制备可用于合成抗溃疡剂的中间体的新方法。本发明提供了制备与常规方法相比能够以高产率获得高纯度化合物，降低生产成本/时间的抗溃疡中间体的方法。

10. 发明授权

US07560760B2 Ferroelectric memory devices having expanded plate lines 失效
标题翻译：具有扩展板线的铁电存储器件
公开(公告)号：US07560760B2
公开(公告)日：2009-07-14
申请号：US11859958
申请日：2007-09-24
申请人： Hyun-Ho Kim , Dong-Jin Jung , Ki-Nam Kim , Sang-Don Nam , Kyu-Mann Lee
发明人： Hyun-Ho Kim , Dong-Jin Jung , Ki-Nam Kim , Sang-Don Nam , Kyu-Mann Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.
摘要翻译：铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，被布置为在行和列方向上的多个行和列。多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过绝缘层中的开口。在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。相邻行中的铁电电容器可以共享公共铁电电介质区域。讨论相关的制造方法。

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