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1. 发明申请

US20170054070A1 Magnetoresistive Random Access Memory Device and Method of Manufacturing the Same 审中-公开
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US20170054070A1
公开(公告)日：2017-02-23
申请号：US15146355
申请日：2016-05-04
申请人： Jung-Hoon Bak , Myoung-Su Son , Jae-Chul Shim , Gwan-Hyeob Koh , Yoon-Jong Song
发明人： Jung-Hoon Bak , Myoung-Su Son , Jae-Chul Shim , Gwan-Hyeob Koh , Yoon-Jong Song
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12 , H01L43/08
CPC分类号： H01L43/02 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
摘要翻译：在制造MRAM器件的方法中，在衬底上形成包括下电极，MTJ结构和顺序层叠的上电极的存储单元。在衬底上形成包括依次堆叠的覆盖层，牺牲层和蚀刻停止层的保护层结构以覆盖存储单元。在保护层结构上形成绝缘中间层。形成绝缘中间层以形成露出保护层结构的开口。暴露的保护层结构被部分去除以暴露上电极。在暴露的上电极上形成布线以填充开口。

2. 发明申请

US20160020384A1 MAGNETIC MEMORY DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：磁记忆体装置及其形成方法
公开(公告)号：US20160020384A1
公开(公告)日：2016-01-21
申请号：US14656659
申请日：2015-03-12
申请人： Dae-Eun JEONG , Sang-Yong KIM , Yoon-Jong SONG
发明人： Dae-Eun JEONG , Sang-Yong KIM , Yoon-Jong SONG
IPC分类号： H01L43/08 , G11C11/16 , H01L43/02
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1675 , G11C2013/0083 , H01L43/02 , H01L43/12
摘要： Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a magnetic tunnel junction pattern located on a substrate and including magnetic patterns and a tunnel barrier pattern located between the magnetic patterns, and a first crystallinity conserving pattern located on the magnetic tunnel junction pattern and having a higher crystallization temperature than the magnetic patterns. The first crystallinity conserving pattern is amorphous.
摘要翻译：提供一种磁存储器件及其形成方法。磁存储器件包括位于衬底上的磁性隧道结图案，其包括磁性图案和位于磁性图案之间的隧道势垒图案，以及位于磁性隧道结图案上的第一结晶保存图案，并且具有比磁性图案。第一个结晶保存图案是无定形的。

3. 发明申请

US20120175580A1 VARIABLE RESISTANCE MEMORY 审中-公开
标题翻译：可变电阻记忆
公开(公告)号：US20120175580A1
公开(公告)日：2012-07-12
申请号：US13430042
申请日：2012-03-26
申请人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

4. 发明授权

US07932102B2 Phase change memory and method of fabricating the same 失效
标题翻译：相变记忆及其制造方法
公开(公告)号：US07932102B2
公开(公告)日：2011-04-26
申请号：US12314884
申请日：2008-12-18
申请人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L21/00 , H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

5. 发明授权

US07888667B2 Phase change memory device 失效
标题翻译：相变存储器件
公开(公告)号：US07888667B2
公开(公告)日：2011-02-15
申请号：US12008125
申请日：2008-01-09
申请人： Yoon-Jong Song , Se-Ho Lee , Ki-Nam Kim , Su-Youn Lee , Jae-Hyun Park
发明人： Yoon-Jong Song , Se-Ho Lee , Ki-Nam Kim , Su-Youn Lee , Jae-Hyun Park
IPC分类号： H01L47/00 , H01L21/00 , G11C11/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/1683 , Y10S438/90
摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.
摘要翻译：相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。加热电极设置在使基板穿过模具层的开口中。加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。填充绝缘图案填充由加热电极的侧壁围绕的空白区域。相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。相变材料图案接触加热电极的侧壁的顶表面。

6. 发明授权

US07696508B2 Phase change memory devices having dual lower electrodes 有权
标题翻译：具有双下电极的相变存储器件
公开(公告)号：US07696508B2
公开(公告)日：2010-04-13
申请号：US11932781
申请日：2007-10-31
申请人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
发明人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
IPC分类号： H01L29/43
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1675
摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.
摘要翻译：半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。包括通过下层间绝缘层并露出衬底的开口。掩埋绝缘图案设置在开口中。依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。还提供了制造半导体器件的方法。

7. 发明申请

US20090127538A1 Phase-Changeable Memory Devices Having Reduced Susceptibility to Thermal Interference 有权
标题翻译：相位可变的存储器件降低了对热干扰的敏感性
公开(公告)号：US20090127538A1
公开(公告)日：2009-05-21
申请号：US12265262
申请日：2008-11-05
申请人： Kyung-Chang Ryoo , Jong-Woo Ko , Yoon-Jong Song
发明人： Kyung-Chang Ryoo , Jong-Woo Ko , Yoon-Jong Song
IPC分类号： H01L47/00
CPC分类号： H01L45/143 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , Y10S257/903
摘要： A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.
摘要翻译：非易失性存储器阵列包括相变存储元件的阵列，它们通过在可相变存储元件阵列之间延伸的至少第一电绝缘区域彼此电绝缘。第一电绝缘区域中包括多个空隙。这些空隙中的每一个在非易失性存储器阵列中相应的一对相位可变存储单元之间延伸，并且总体上空隙在第一电绝缘区域中形成一组空隙。

8. 发明申请

US20090101881A1 SEMICONDUCTOR DEVICES HAVING PHASE CHANGE MEMORY CELLS, ELECTRONIC SYSTEMS EMPLOYING THE SAME AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有相变记忆体的半导体器件，使用其的电子系统及其制造方法
公开(公告)号：US20090101881A1
公开(公告)日：2009-04-23
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L45/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

9. 发明申请

US20080099753A1 PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有双下电极的相变存储器件及其制造方法
公开(公告)号：US20080099753A1
公开(公告)日：2008-05-01
申请号：US11932781
申请日：2007-10-31
申请人： Yoon-Jong SONG , Kyung-Chang RYOO , Dong-Won LIM
发明人： Yoon-Jong SONG , Kyung-Chang RYOO , Dong-Won LIM
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1675
摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.
摘要翻译：半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。包括通过下层间绝缘层并露出衬底的开口。掩埋绝缘图案设置在开口中。依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。还提供了制造半导体器件的方法。

10. 发明申请

US20060108622A1 Ferroelectric integrated circuit devices having an oxygen penetration path and methods for manufacturing the same 失效
公开(公告)号：US20060108622A1
公开(公告)日：2006-05-25
申请号：US11248629
申请日：2005-10-12
申请人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
发明人： Heung-jin Joo , Ki-nam Kim , Yoon-jong Song
IPC分类号： H01L29/94 , H01L21/00
CPC分类号： H01L28/55 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

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