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1. 发明授权

US08288289B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08288289B2
公开(公告)日：2012-10-16
申请号：US13016228
申请日：2011-01-28
申请人： Jun-Ho Jeong , Jang-Eun Lee , Se-Chung Oh , Suk-Hun Choi , Jea-Hyoung Lee , Woo-Jin Kim , Woo-Chang Lim
发明人： Jun-Ho Jeong , Jang-Eun Lee , Se-Chung Oh , Suk-Hun Choi , Jea-Hyoung Lee , Woo-Jin Kim , Woo-Chang Lim
IPC分类号： H01L21/302
CPC分类号： H01L21/28
摘要： A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.
摘要翻译：一种制造半导体器件的方法，所述方法包括提供衬底; 在衬底上形成下层; 在下层上形成牺牲层; 通过图案化所述牺牲层在所述牺牲层中形成开口，使得所述开口暴露所述下层的预定区域; 在开口中形成掩模层; 通过部分或完全氧化掩模层形成氧化物掩模; 去除牺牲层; 并使用氧化物掩模作为蚀刻掩模蚀刻下层以形成下层图案。

2. 发明授权

US08168521B2 Methods of manufacturing semiconductor devices having low resistance buried gate structures 有权
标题翻译：制造具有低电阻掩埋栅极结构的半导体器件的方法
公开(公告)号：US08168521B2
公开(公告)日：2012-05-01
申请号：US12725743
申请日：2010-03-17
申请人： In-Sang Jeon , Si-Hyung Lee , Jong-Ryeol Yoo , Yu-Ghun Shin , Suk-Hun Choi
发明人： In-Sang Jeon , Si-Hyung Lee , Jong-Ryeol Yoo , Yu-Ghun Shin , Suk-Hun Choi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4236 , H01L21/67207 , H01L21/823437 , H01L21/823456 , H01L29/66621 , H01L29/78
摘要： In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.
摘要翻译：在制造半导体器件的方法中，在衬底的有源区中形成凹部。在第一凹部中形成栅极绝缘层。在栅绝缘层上形成阻挡层。在阻挡层上形成具有第一电阻的预成核层。将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。在成核层上形成导电层。部分蚀刻导电层，成核层，势垒层和栅极绝缘层，以形成包括栅极绝缘层图案，势垒层图案，成核层图案和导电层图案的掩埋栅极结构。

3. 发明授权

US08124526B2 Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same 失效
标题翻译：形成薄铁电体层的方法和制造其的半导体器件的制造方法
公开(公告)号：US08124526B2
公开(公告)日：2012-02-28
申请号：US12503440
申请日：2009-07-15
申请人： Suk-Hun Choi , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon
发明人： Suk-Hun Choi , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon
IPC分类号： H01L21/4763
CPC分类号： H01L27/11507 , H01L21/3105 , H01L21/31053 , H01L28/55
摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.
摘要翻译：在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

4. 发明申请

US20110306173A1 METHOD FABRICATING SEMICONDUCTOR DEVICE USING MULTIPLE POLISHING PROCESSES 有权
标题翻译：使用多个抛光工艺制作半导体器件的方法
公开(公告)号：US20110306173A1
公开(公告)日：2011-12-15
申请号：US13084657
申请日：2011-04-12
申请人： Jun-Soo BAE , Suk-Hun CHOI , Won-Jun LEE , Joon-Sang PARK
发明人： Jun-Soo BAE , Suk-Hun CHOI , Won-Jun LEE , Joon-Sang PARK
IPC分类号： H01L21/02
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/141
摘要： A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.
摘要翻译：制造相变存储器件的方法包括使用第一，第二和第三抛光工艺。第一抛光工艺使用第一牺牲层形成第一接触部分，并且第二抛光工艺使用第二牺牲层形成相变材料图案。在去除第一和第二牺牲层以暴露第一接触部分的相应突出结构和相变材料图案之后，使用第三抛光工艺来使用绝缘层作为抛光停止层来抛光所得的突出结构。

5. 发明授权

US08034705B2 Method of forming a seam-free tungsten plug 有权
标题翻译：形成无缝钨丝塞的方法
公开(公告)号：US08034705B2
公开(公告)日：2011-10-11
申请号：US12460318
申请日：2009-07-16
申请人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Ju-Young Jung
发明人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Ju-Young Jung
IPC分类号： H01L21/4763
CPC分类号： H01L21/76888 , H01L21/76879 , H01L21/76883 , H01L27/24
摘要： A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.
摘要翻译：插头包括第一绝缘中间层，钨图案和氧化钨图案。第一绝缘中间层具有在基板上形成的接触孔。钨图案形成在接触孔中。钨图案具有比第一绝缘中间层的上表面低的顶表面。氧化钨图案形成在接触孔和钨图案上。氧化钨图案具有水平面。

6. 发明授权

US07678625B2 Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics 有权
标题翻译：制造半导体器件的方法包括具有改进的缺陷密度和表面粗糙度特性的沟道层
公开(公告)号：US07678625B2
公开(公告)日：2010-03-16
申请号：US11962742
申请日：2007-12-21
申请人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
发明人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
IPC分类号： H01L21/84
CPC分类号： H01L21/02675 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/78
摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.
摘要翻译：制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。单晶半导体层包括从其表面延伸的突起。在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。还讨论了制造叠层半导体存储器件的相关方法。

7. 发明申请

US20100009531A1 METHODS OF FORMING A CONTACT STRUCTURE 有权
标题翻译：形成接触结构的方法
公开(公告)号：US20100009531A1
公开(公告)日：2010-01-14
申请号：US12499832
申请日：2009-07-09
申请人： Suk-Hun CHOI , Chang-Ki HONG , Hyun-Jun SIM , Yoon-Ho SON
发明人： Suk-Hun CHOI , Chang-Ki HONG , Hyun-Jun SIM , Yoon-Ho SON
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/28273 , H01L21/76802 , H01L21/76844 , H01L21/76885 , H01L23/485 , H01L23/53257 , H01L27/11541 , H01L27/11548 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact hole. A planarization process is performed on the metal layer until the first insulation layer is exposed to form a first contact. A second contact is grown from the first contact. The second contact is formed without performing a photolithography process and an etching process to prevent misalignments.
摘要翻译：在形成接触结构的方法中，在基板上形成包括第一接触孔的第一绝缘层。形成包括钨的金属层以填充第一接触孔。在金属层上进行平坦化处理，直到暴露第一绝缘层以形成第一接触。从第一个联系人生长第二个联系人。形成第二接触，而不进行光刻工艺和蚀刻工艺以防止未对准。

8. 发明申请

US20090146304A1 CARBON NANOTUBE INTEGRATED CIRCUIT DEVICES AND METHODS OF FABRICATION THEREFOR USING PROTECTED CATALYST LAYERS 审中-公开
标题翻译：碳纳米管集成电路器件及其使用受保护的催化层的制造方法
公开(公告)号：US20090146304A1
公开(公告)日：2009-06-11
申请号：US11924308
申请日：2007-10-25
申请人： Yoon-ho Son , Sun-woo Lee , Young-moon Choi , Seong-ho Moon , Hong-sik Yoon , Suk-hun Choi , Kyung-rae Byun
发明人： Yoon-ho Son , Sun-woo Lee , Young-moon Choi , Seong-ho Moon , Hong-sik Yoon , Suk-hun Choi , Kyung-rae Byun
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76879 , H01L21/76834 , H01L21/76849 , H01L21/7685 , H01L21/76876 , H01L23/5226 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit device is provided. The method includes sequentially forming a lower interconnection layer, a catalyst layer, and a buffer layer on a semiconductor substrate, forming an interlayer dielectric layer to cover the buffer layer, forming a contact hole through the interlayer dielectric layer so that a top surface of the buffer layer may be partially exposed, removing a portion of the buffer layer exposed by the contact hole so that a top surface of the catalyst layer may be exposed, and growing carbon nanotubes from a portion of the catalyst layer exposed by the contact hole so that the contact hole may be filled with the carbon nanotubes.
摘要翻译：提供一种制造集成电路器件的方法。该方法包括在半导体衬底上依次形成下互连层，催化剂层和缓冲层，形成覆盖缓冲层的层间电介质层，形成穿过层间电介质层的接触孔，缓冲层可以部分地暴露，去除由接触孔暴露的缓冲层的一部分，使得催化剂层的顶表面可能被暴露，并且从催化剂层的由接触孔暴露的部分生长碳纳米管，使得可以用碳纳米管填充接触孔。

9. 发明申请

US20080128853A1 Non-Volatile Memory Devices with Discrete Resistive Memory Material Regions and Methods of Fabricating the Same 审中-公开
标题翻译：具有离散电阻记忆材料区域的非易失性存储器件及其制造方法
公开(公告)号：US20080128853A1
公开(公告)日：2008-06-05
申请号：US11939041
申请日：2007-11-13
申请人： Suk-hun Choi , In-gyu Baek , Jun-young Lee , Jung-hyeon Kim , Chang-ki Hong , Yoon-ho Son
发明人： Suk-hun Choi , In-gyu Baek , Jun-young Lee , Jung-hyeon Kim , Chang-ki Hong , Yoon-ho Son
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L28/20 , H01L45/1233 , H01L45/146 , H01L45/1683
摘要： A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.
摘要翻译：半导体存储器件包括半导体衬底上的第一导电线，第一导线上的层间绝缘层，层间绝缘层上的第二导线，以及穿过层间绝缘层的孔中的存储单元，其中，第二导线交叉，存储单元包括设置在孔中并电连接在第一和第二导线之间的分立的电阻性存储器材料区域。电阻性存储器材料区域可以基本上包含在孔内。在一些实施例中，电阻性存储器材料区域和层间绝缘层之间的接触基本上限于孔中的层间绝缘层的侧壁。

10. 发明授权

US07291556B2 Method for forming small features in microelectronic devices using sacrificial layers 失效
标题翻译：在使用牺牲层的微电子器件中形成小特征的方法
公开(公告)号：US07291556B2
公开(公告)日：2007-11-06
申请号：US10873388
申请日：2004-06-22
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并且在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

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