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1. 发明授权

US10468103B2 Integrated circuit devices including separate memory cells on separate regions of individual substrate 有权
公开(公告)号：US10468103B2
公开(公告)日：2019-11-05
申请号：US15826031
申请日：2017-11-29
申请人： Sung-woo Kim , Jae-kyu Lee , Ki-seok Suh , Hyeong-sun Hong , Yoo-sang Hwang , Gwan-hyeob Koh
发明人： Sung-woo Kim , Jae-kyu Lee , Ki-seok Suh , Hyeong-sun Hong , Yoo-sang Hwang , Gwan-hyeob Koh
IPC分类号： G11C14/00 , H01L45/00 , H01L29/08 , H01L27/108 , H01L23/528 , H01L29/423 , H01L43/08 , H01L43/02 , H01L43/12 , H01L27/24 , H01L27/22 , H01L27/105 , H01L27/02 , G11C7/10 , G11C11/00
摘要： An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

2. 发明申请

US20180342669A1 METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR CHIP INCLUDING THE SAME 审中-公开
公开(公告)号：US20180342669A1
公开(公告)日：2018-11-29
申请号：US15856256
申请日：2017-12-28
申请人： Dae-Shik KIM , Jeong-Heon PARK , Gwan-Hyeob KOH
发明人： Dae-Shik KIM , Jeong-Heon PARK , Gwan-Hyeob KOH
IPC分类号： H01L43/12 , H01L43/08 , H01L43/02 , H01L27/22 , G11C11/16
CPC分类号： H01L43/12 , G11C11/161 , H01L27/228 , H01L29/41791 , H01L43/02 , H01L43/08
摘要： In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

3. 发明申请

US20180158526A1 INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING SAME 审中-公开
公开(公告)号：US20180158526A1
公开(公告)日：2018-06-07
申请号：US15826031
申请日：2017-11-29
申请人： Sung-woo KIM , Jae-kyu LEE , Ki-seok SUH , Hyeong-sun HONG , Yoo-sang HWANG , Gwan-hyeob KOH
发明人： Sung-woo KIM , Jae-kyu LEE , Ki-seok SUH , Hyeong-sun HONG , Yoo-sang HWANG , Gwan-hyeob KOH
IPC分类号： G11C14/00 , H01L27/22 , H01L29/08 , H01L27/108 , H01L23/528 , H01L29/423 , H01L45/00 , H01L43/08 , H01L43/02 , H01L43/12 , H01L27/24
摘要： An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

4. 发明申请

US20180012933A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180012933A1
公开(公告)日：2018-01-11
申请号：US15712130
申请日：2017-09-21
申请人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
发明人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
IPC分类号： H01L27/22 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

5. 发明申请

US20120236627A1 MULTI-LEVEL MEMORY DEVICES AND METHODS OF OPERATING THE SAME 有权
标题翻译：多级存储器件及其操作方法
公开(公告)号：US20120236627A1
公开(公告)日：2012-09-20
申请号：US13487463
申请日：2012-06-04
申请人： Gwan-Hyeob Koh , Dae-Won Ha
发明人： Gwan-Hyeob Koh , Dae-Won Ha
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C11/56 , G11C13/0004
摘要： The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.
摘要翻译：本发明提供了一种多级存储装置及其操作方法。该装置包括存储器结构，其中电阻值在其最小值附近的分布密度高于围绕其最大值的分布密度。

6. 发明授权

US08026543B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US08026543B2
公开(公告)日：2011-09-27
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L27/108 , H01L47/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.
摘要翻译：相变存储器件具有氧化阻挡层以防止存储器细胞污染或氧化。在一个实施例中，半导体存储器件包括设置在半导体衬底上的成型层，相变材料图案和电绝缘材料的氧化屏障。成型层在其上部具有突出部。可相变材料图案的一部分覆盖模制层的突起，并且相变材料图案的另一部分延伸穿过突出部。氧化屏障的电绝缘材料可以覆盖相变材料图案和/或延伸并且覆盖模制层的突起和设置在突起上的相变材料图案的部分邻接的整个区域。

7. 发明授权

US07112492B2 Methods of fabricating semiconductor devices with scalable two transistor memory cells 失效
标题翻译：用可扩展的双晶体管存储单元制造半导体器件的方法
公开(公告)号：US07112492B2
公开(公告)日：2006-09-26
申请号：US11040229
申请日：2005-01-21
申请人： Su-Jin Ahn , Gwan-Hyeob Koh , Hyoung-Joon Kim
发明人： Su-Jin Ahn , Gwan-Hyeob Koh , Hyoung-Joon Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11543 , H01L29/42324 , H01L29/7881
摘要： Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.
摘要翻译：公开了具有可伸缩的双晶体管存储单元的半导体器件及其制造方法。半导体器件包括其上具有第一，第二和第三隔离层的半导体衬底。第一和第二隔离层间隔开以限定它们之间的第一有源区，并且第二隔离层和第三隔离层同样隔开以在它们之间形成第二有源区。在每个有源区域上提供一个单元栅极，该栅极电介质层，存储节点，多个隧道结屏障和源层依次堆叠。该装置还包括围绕电池栅极的每个侧壁的至少一部分的第一和第二控制线。电介质层可以插在电池栅极的侧壁和围绕它的控制线之间。数据线连接到单元门。

8. 发明授权

US06753227B2 Method of fabricating MOS transistors 有权
标题翻译：制造MOS晶体管的方法
公开(公告)号：US06753227B2
公开(公告)日：2004-06-22
申请号：US10437881
申请日：2003-05-13
申请人： Chang-Hyun Cho , Gwan-Hyeob Koh , Ki-Nam Kim
发明人： Chang-Hyun Cho , Gwan-Hyeob Koh , Ki-Nam Kim
IPC分类号： H01L21336
CPC分类号： H01L21/823807 , H01L21/28061 , H01L21/823892 , H01L29/4933
摘要： A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.
摘要翻译：提供一种制造MOS晶体管的方法。根据该方法，将快速热退火应用于具有掺杂有良好杂质离子和沟道杂质离子的有源区的半导体衬底。因此，在注入阱和通道杂质离子期间，通过快速热退火可以固化由植入产生的结晶缺陷。

9. 发明授权

US06335233B1 Method for fabricating MOS transistor 失效
标题翻译：制造MOS晶体管的方法
公开(公告)号：US06335233B1
公开(公告)日：2002-01-01
申请号：US09347822
申请日：1999-07-02
申请人： Chang-Hyun Cho , Gwan-Hyeob Koh , Mi-Hyang Lee , Dae-Won Ha
发明人： Chang-Hyun Cho , Gwan-Hyeob Koh , Mi-Hyang Lee , Dae-Won Ha
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823807 , H01L21/823892 , H01L29/0847 , H01L29/1079 , H01L29/7833
摘要： A first conductive impurity ion is implanted into a semiconductor substrate to form a well area on which a gate electrode is formed. A first non-conductive impurity is implanted into the well area on both sides of the gate electrode to control a substrate defect therein and to form a first precipitate area to a first depth. A second conductive impurity ion is implanted into the well area on both sides of the gate electrode, so that a source/drain area is formed to a second depth being relatively shallower than the first depth. A second non-conductive impurity is implanted into the source/drain area so as to control a substrate defect therein and to form a second precipitate area. As a result, substrate defects such as dislocation, extended defect, and stacking fault are isolated from a P-N junction area, thereby forming a stable P-N junction.
摘要翻译：将第一导电杂质离子注入到半导体衬底中以形成其上形成栅电极的阱区。将第一非导电杂质注入到栅极两侧的阱区中以控制其中的衬底缺陷并形成第一深度的第一沉淀区。将第二导电杂质离子注入到栅极两侧的阱区中，使得源/漏区形成为比第一深度相对浅的第二深度。将第二非导电杂质注入源/漏区，以便控制其中的衬底缺陷并形成第二沉淀区。结果，从P-N结区域隔离诸如位错，延伸缺陷和堆垛层错的基板缺陷，从而形成稳定的P-N结。

10. 发明授权

US09691459B2 Semiconductor memory device including shorted variable resistor element of memory cell 有权
公开(公告)号：US09691459B2
公开(公告)日：2017-06-27
申请号：US15249845
申请日：2016-08-29
申请人： Bo-young Seo , Suk-soo Pyo , Gwan-hyeob Koh , Yong-kyu Lee , Dae-shik Kim
发明人： Bo-young Seo , Suk-soo Pyo , Gwan-hyeob Koh , Yong-kyu Lee , Dae-shik Kim
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C7/14 , G11C11/1673 , G11C13/004 , G11C29/028 , G11C29/50008 , G11C2013/0054 , G11C2029/4402
摘要： A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.

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