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1. 发明授权

US6097078A Method for forming triple well in semiconductor device 有权
标题翻译：在半导体器件中形成三阱的方法
公开(公告)号：US6097078A
公开(公告)日：2000-08-01
申请号：US275908
申请日：1999-03-24
申请人： Sang-pil Sim , Won-saong Lee
发明人： Sang-pil Sim , Won-saong Lee
IPC分类号： H01L21/8242 , H01L27/092 , H01L27/02 , H01L21/8238
CPC分类号： H01L27/10894 , H01L27/0928
摘要： A method is provided for forming a triple well of a semiconductor memory device, where a second well of a second conductive type encloses a second well of a first conductive type. A single mask is used for ion implanting the base of the enclosing well and also the entire enclosed well, which inherently avoids misalignment. Additional doping is provided to the location where the sidewalls of the enclosing well join its base. This is accomplished either by a second, deeper ion implant of the sidewalls, or by ion implanting the base at an angle and rotating it, or both. Alternately, the single mask pattern is processed between the ion implantation steps to alter its width.
摘要翻译：提供了一种用于形成半导体存储器件的三阱的方法，其中第二导电类型的第二阱包围第一导电类型的第二阱。单个掩模用于离子注入封闭井的底部以及整个封闭的井，这固有地避免了未对准。另外的掺杂被提供到封闭井的侧壁连接其底部的位置。这可以通过侧壁的第二更深的离子注入，或通过以一定角度离子注入基底并使其旋转或两者来实现。或者，在离子注入步骤之间处理单个掩模图案以改变其宽度。

2. 发明授权

US5915189A Manufacturing method for semiconductor memory device having a storage node with surface irregularities 失效
标题翻译：具有具有表面不规则的存储节点的半导体存储器件的制造方法
公开(公告)号：US5915189A
公开(公告)日：1999-06-22
申请号：US918619
申请日：1997-08-22
申请人： Sang-pil Sim
发明人： Sang-pil Sim
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90
摘要： A method for forming a storage electrode having increased area in a highly-integrated semiconductor device. In the method, a trench is formed in a thick insulating interlayer deposited on a semiconductor substrate. Hemispherical grains are formed on the surface of the trench to increase the surface area of the trench. A conductive layer for forming a storage electrode is formed in the surface of the trench. The conductive layer is patterned with a CMP process or etch back process to form a storage electrode. Forming a capacitor dielectric film over the electrode and a plate electrode over the film completes the process.
摘要翻译：一种用于形成在高度集成的半导体器件中具有增加的面积的存储电极的方法。在该方法中，在沉积在半导体衬底上的厚绝缘层中形成沟槽。在沟槽的表面上形成半球状晶粒以增加沟槽的表面积。用于形成存储电极的导电层形成在沟槽的表面中。用CMP工艺或回蚀工艺对导电层进行构图以形成存储电极。在电极上形成电容器电介质膜，并在膜上形成平板电极完成该过程。

3. 发明授权

US5399518A Method for manufacturing a multiple walled capacitor of a semiconductor device 失效
标题翻译：制造半导体器件的多层电容器的方法
公开(公告)号：US5399518A
公开(公告)日：1995-03-21
申请号：US91369
申请日：1993-07-15
申请人： Sang-pil Sim , Joo-young Yun , Chang-kyu Hwang , Jeong-gil Lee , Chul-ho Shin , Won-woo Lee
发明人： Sang-pil Sim , Joo-young Yun , Chang-kyu Hwang , Jeong-gil Lee , Chul-ho Shin , Won-woo Lee
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91 , H01L28/92
摘要： A method for manufacturing a double-cylindrical storage electrode of a capacitor of a semiconductor memory device, utilizes an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder. After forming a conductive structure on a semiconductor substrate, an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder are formed on the conductive structure. Then, the conductive structure is anisotropically etched using the outer and inner etching masks, thereby forming a double-cylindrical first electrode. Since a double-cylindrical storage electrode can be obtained from a single conductive layer, the influence of native oxidation circumvented. In addition, the double-cylindrical storage electrode of the capacitor according to the present invention decreases the risk of structural fragmenting because the electrode is obtained from one material layer, instead of a combination of layers as is conventionally-known. Also, the storage electrode of the present invention has no sharp edges, so that leakage current can be minimized or avoided.
摘要翻译：一种用于制造半导体存储器件的电容器的双圆柱形存储电极的方法，利用用于形成外圆筒的外蚀刻掩模和用于形成内筒的内蚀刻掩模。在半导体衬底上形成导电结构之后，在导电结构上形成用于形成外筒的外蚀刻掩模和用于形成内筒的内蚀刻掩模。然后，使用外蚀刻掩模和内蚀刻掩模对导电结构进行各向异性蚀刻，从而形成双圆柱形第一电极。由于可以从单个导电层获得双圆柱形存储电极，因此避免了天然氧化的影响。此外，根据本发明的电容器的双圆柱形存储电极降低了结构碎裂的风险，因为电极是从一个材料层获得的，而不是如传统已知的层的组合。此外，本发明的存储电极没有尖锐的边缘，使得可以最小化或避免泄漏电流。

4. 发明授权

US07075142B2 Cell arrays of memory devices having extended source strapping regions 失效
标题翻译：具有扩展源束带区域的存储器件的单元阵列
公开(公告)号：US07075142B2
公开(公告)日：2006-07-11
申请号：US10988785
申请日：2004-11-15
申请人： Sang-pil Sim , Chan-kwang Park
发明人： Sang-pil Sim , Chan-kwang Park
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/115
摘要： A cell array of a flash memory device includes extended source strapping regions. The cell array includes a device isolation layer and active regions. The device isolation layer is formed in a semiconductor substrate, and the active regions are defined by the device isolation layer. Word lines cross over the active regions, and a common source line electrically connects the active regions between two word lines of word line pairs. A source strapping region is defined between the two word lines of the word line pairs. The source strapping region crosses multiple active regions.
摘要翻译：快闪存储器件的单元阵列包括扩展的源束带区域。电池阵列包括器件隔离层和有源区。器件隔离层形成在半导体衬底中，有源区由器件隔离层限定。字线跨越有源区，并且公共源极线电连接字线对的两个字线之间的有源区。在字线对的两个字线之间定义源带束带区域。源束带区域穿过多个活动区域。

5. 发明授权

US6117773A Methods of fabricating microelectronic devices having increased impurity concentration between a metal silicide contact surface 失效
标题翻译：制造在金属硅化物接触表面之间具有增加的杂质浓度的微电子器件的方法
公开(公告)号：US6117773A
公开(公告)日：2000-09-12
申请号：US84144
申请日：1998-05-26
申请人： Sang-pil Sim
发明人： Sang-pil Sim
IPC分类号： H01L21/28 , H01L21/265 , H01L21/285 , H01L21/768 , H01L29/36 , H01L29/417 , H01L29/45 , H01L29/78 , H01L21/44
CPC分类号： H01L29/36 , H01L21/26513 , H01L21/28518 , H01L21/76877 , H01L29/456
摘要： A microelectronic device includes a first region having a first conductivity type. A second region having a second conductivity type contacts the first region at a junction therebetween. A metal silicide region contacts the second region at a contact surface apart from the junction. Impurities of the second conductivity type in the second region are concentrated between the contact surface and the junction, for example, in one or more subregions disposed between the contact surface and the junction. The subregions may include a first subregion adjacent the junction formed by an ion implantation at a first energy level, and a second subregion disposed between the first subregion and the contact surface formed by a second ion implantation at a different energy level. Related fabrication methods are also provided.
摘要翻译：微电子器件包括具有第一导电类型的第一区域。具有第二导电类型的第二区域在它们之间的接合处接触第一区域。金属硅化物区域在与结点分开的接触表面处接触第二区域。第二区域中的第二导电类型的杂质集中在接触表面和接合部之间，例如在设置在接触表面和接合部之间的一个或多个子区域中。所述子区域可以包括邻近由第一能级的离子注入形成的结的第一子区域，以及设置在第一子区域和由不同能级的第二离子注入形成的接触表面之间的第二子区域。还提供了相关的制造方法。

6. 发明授权

US5597763A Method for manufacturing a semiconductor wiring structure including a self-aligned contact hole 失效
标题翻译：包括自对准接触孔的半导体布线结构的制造方法
公开(公告)号：US5597763A
公开(公告)日：1997-01-28
申请号：US427855
申请日：1995-04-26
申请人： Sang-pil Sim
发明人： Sang-pil Sim
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L23/52 , H01L23/528 , H01L27/088 , H01L27/10 , H01L27/108 , H01L21/28
CPC分类号： H01L21/768 , H01L23/528 , H01L2924/0002
摘要： In a highly integrated semiconductor wiring structure having a plurality of wiring layers and a self-aligned contact hole formed therebetween, the wiring layer is formed such that a portion where a contact hole will be formed is formed to a first wiring width and a remaining portion is formed to a second wiring width being wider than the first wiring width. In the method for manufacturing such a structure, the contact hole is formed in self-alignment fashion, and thus, a short which may occur due to misalignment can be prevented.
摘要翻译：在具有形成在其间的多个布线层和自对准接触孔的高度集成的半导体布线结构中，布线层形成为使得将形成接触孔的部分形成为第一布线宽度，并且剩余部分形成为比第一布线宽度宽的第二布线宽度。在制造这种结构的方法中，接触孔以自对准的方式形成，因此可以防止由于未对准而发生的短路。

7. 发明授权

US5447878A Method for manufacturing a semiconductor memory device having a capacitor with increased effective area 失效
标题翻译：一种制造具有增加有效面积的电容器的半导体存储器件的方法
公开(公告)号：US5447878A
公开(公告)日：1995-09-05
申请号：US112331
申请日：1993-08-27
申请人： Young-woo Park , Jun-yong No , Sang-pil Sim
发明人： Young-woo Park , Jun-yong No , Sang-pil Sim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92 , H01L28/84
摘要： A storage electrode of a capacitor of a semiconductor memory device and a method for manufacturing the same are disclosed. A first electrode of the capacitor comprises a main electrode having a plurality of microtrenches and micropillars formed therein, an outer wall surrounding the microtrenches and micropillars, a granular silicon layer formed on an outer sidewall of the outer wall, and a column electrode supporting the main electrode and electrically connecting the main electrode to a source region of a transistor of the semiconductor device. The first electrode preferably has a horizontally fin-structured auxiliary electrode formed underneath the main electrode and electrically connected to the column electrode of the first electrode. The capacitor may be formed by using an etching end-point detection layer and an HSG polysilicon layer. The effective surface area of the storage electrode of a capacitor is increased to thereby obtain adequate cell capacitance. Also, uniform shapes of the storage electrodes are preferably obtained to thereby attain uniform cell capacitance.
摘要翻译：公开了一种半导体存储器件的电容器的存储电极及其制造方法。电容器的第一电极包括主电极，其具有形成在其中的多个微电影和微透镜，围绕微电极和微透镜的外壁，形成在外壁的外侧壁上的粒状硅层和支撑主体的柱电极电极并将主电极电连接到半导体器件的晶体管的源极区域。第一电极优选具有形成在主电极下方的水平翅片结构的辅助电极，并且电连接到第一电极的列电极。可以通过使用蚀刻端点检测层和HSG多晶硅层来形成电容器。电容器的存储电极的有效表面积增加，从而获得足够的电池电容。此外，优选地获得存储电极的均匀形状，从而获得均匀的电池电容。

8. 发明申请

US20050173743A1 Cell arrays of memory devices having extended source strapping regions 失效
标题翻译：具有扩展源束带区域的存储器件的单元阵列
公开(公告)号：US20050173743A1
公开(公告)日：2005-08-11
申请号：US10988785
申请日：2004-11-15
申请人： Sang-pil Sim , Chan-kwang Park
发明人： Sang-pil Sim , Chan-kwang Park
IPC分类号： H01L21/8247 , H01L21/8239 , H01L27/105 , H01L27/108 , H01L27/115
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/115
摘要： A cell array of a flash memory device includes extended source strapping regions. The cell array includes a device isolation layer and active regions. The device isolation layer is formed in a semiconductor substrate, and the active regions are defined by the device isolation layer. Word lines cross over the active regions, and a common source line electrically connects the active regions between two word lines of word line pairs. A source strapping region is defined between the two word lines of the word line pairs. The source strapping region crosses multiple active regions.
摘要翻译：快闪存储器件的单元阵列包括扩展的源束带区域。电池阵列包括器件隔离层和有源区。器件隔离层形成在半导体衬底中，有源区由器件隔离层限定。字线跨越有源区，并且公共源极线电连接字线对的两个字线之间的有源区。在字线对的两个字线之间定义源带束带区域。源束带区域穿过多个活动区域。

9. 发明授权

US6025617A Microelectronic devices having increased impurity concentration between a metal silicide contact surface 失效
标题翻译：微电子器件在金属硅化物接触表面之间具有增加的杂质浓度
公开(公告)号：US6025617A
公开(公告)日：2000-02-15
申请号：US899554
申请日：1997-07-24
申请人： Sang-pil Sim
发明人： Sang-pil Sim
IPC分类号： H01L21/28 , H01L21/265 , H01L21/285 , H01L21/768 , H01L29/36 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/80
CPC分类号： H01L29/36 , H01L21/26513 , H01L21/28518 , H01L21/76877 , H01L29/456
摘要： A microelectronic device includes a first region having a first conductivity type. A second region having a second conductivity type contacts the first region at a junction therebetween. A metal silicide region contacts the second region at a contact surface apart from the junction. Impurities of the second conductivity type in the second region are concentrated between the contact surface and the junction, for example, in one or more subregions disposed between the contact surface and the junction. The subregions may include a first subregion adjacent the junction formed by an ion implantation at a first energy level, and a second subregion disposed between the first subregion and the contact surface formed by a second ion implantation at a different energy level. Related fabrication methods are also provided.
摘要翻译：微电子器件包括具有第一导电类型的第一区域。具有第二导电类型的第二区域在它们之间的接合处接触第一区域。金属硅化物区域在与结点分开的接触表面处接触第二区域。第二区域中的第二导电类型的杂质集中在接触表面和接合部之间，例如在设置在接触表面和接合部之间的一个或多个子区域中。所述子区域可以包括邻近由第一能级的离子注入形成的结的第一子区域，以及设置在第一子区域和由不同能级的第二离子注入形成的接触表面之间的第二子区域。还提供了相关的制造方法。

10. 发明授权

US5567989A Highly integrated semiconductor wiring structure 失效
标题翻译：高度集成的半导体布线结构
公开(公告)号：US5567989A
公开(公告)日：1996-10-22
申请号：US280887
申请日：1994-07-27
申请人： Sang-pil Sim
发明人： Sang-pil Sim
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L23/52 , H01L23/528 , H01L27/088 , H01L27/10 , H01L27/108 , H01L23/48
CPC分类号： H01L21/768 , H01L23/528 , H01L2924/0002
摘要： In a highly integrated semiconductor wiring structure having a plurality of wiring layers and a self-aligned contact hole formed therebetween, the wiring layer is formed such that a portion where a contact hole will be formed is formed to a first wiring width and a remaining portion is formed to a second wiring width being wider than the first wiring width. In the method for manufacturing such a structure, the contact hole is formed in self-alignment fashion, and thus, a short which may occur due to misalignment can be prevented.
摘要翻译：在具有形成在其间的多个布线层和自对准接触孔的高度集成的半导体布线结构中，布线层形成为使得将形成接触孔的部分形成为第一布线宽度，并且剩余部分形成为比第一布线宽度宽的第二布线宽度。在制造这种结构的方法中，接触孔以自对准的方式形成，因此可以防止由于未对准而发生的短路。

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