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1. 发明授权

US09164563B2 Processor noise mitigation using differential critical path monitoring 有权
标题翻译：使用差分关键路径监控的处理器噪声抑制
公开(公告)号：US09164563B2
公开(公告)日：2015-10-20
申请号：US13479797
申请日：2012-05-24
申请人： Robert W. Berry, Jr. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
发明人： Robert W. Berry, Jr. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
IPC分类号： G06F1/28 , G06F1/26 , G06F11/30
CPC分类号： G06F1/28 , G06F1/26 , G06F11/3062
摘要： An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
摘要翻译：提供了一种处理器电源噪声抑制方法。在一个方面，该方法包括可操作地耦合到处理器以执行程序操作的中央计算单元。该方法还包括校准电路，其适于确定要用于通过使用检测电路动态执行的比较的处理器上的第一阈值。一种检测电路，适用于动态地监视处理器的系统操作并指示是否违反了第一阈值，还提供了一种适于在一个或多个电压感测测量违反第一阈值时防止电压下降的计数电路。

2. 发明申请

US20130103354A1 DETECTING CROSS-TALK ON PROCESSOR LINKS 有权
标题翻译：检测处理器链接的交叉口
公开(公告)号：US20130103354A1
公开(公告)日：2013-04-25
申请号：US13281097
申请日：2011-10-25
申请人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/30
CPC分类号： G06F9/30145 , G06F9/30 , G06F11/3409 , G06F11/3414 , G06F11/3466 , G06F11/349
摘要： A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.
摘要翻译：多个处理器链路中的第一个处理器链路的多个数据通路中的第一个被确定为对于多个数据通道具有最弱的基本性能测量。经由剩余处理器链路的第一组发送切换数据模式，并且经由剩余处理器链路的第二组发送安静数据模式。如果第一数据线的性能相对于相应的基本性能测量增加，则剩余处理器链路的第一组从剩余处理器链路中消除。如果第一数据通道的性能相对于相应的基本性能测量值降低，则剩余处理器链路的第二组从剩余处理器链路中消除。重复执行上述操作，直到识别出被确定为降低多个数据通道中的第一个数据通道的性能的攻击者处理器链路。

3. 发明申请

US20080312863A1 SYSTEM AND METHOD FOR IMPLEMENTING A PROGRAMMABLE DMA MASTER WITH DATE CHECKING UTILIZING A DRONE SYSTEM CONTROLLER 失效
标题翻译：用于执行可编程DMA主机的系统和方法，日期检查使用DRONE系统控制器
公开(公告)号：US20080312863A1
公开(公告)日：2008-12-18
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, JR. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, JR. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G11C29/00 , G06F19/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

4. 发明授权

US5375091A Method and apparatus for memory dynamic burn-in and test 失效
标题翻译：用于记忆动态老化和测试的方法和装置
公开(公告)号：US5375091A
公开(公告)日：1994-12-20
申请号：US163803
申请日：1993-12-08
申请人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
发明人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
IPC分类号： G11C29/10 , G11C29/50 , G11C13/00
CPC分类号： G11C29/10 , G11C29/50
摘要： A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.
摘要翻译：嵌入在集成处理器芯片中的存储器通过重复地将测试图案写入存储器的数据位置而被动态地受到压力测试，其中高百分比的存储器单元被顺序地写有补充数据，以便在存储器上产生高应力设备。作为存储器的地址位置的数量和存储器数据字的数据位的数量的函数产生测试图案。每次存储器寻址时，测试模式都会旋转。测试图案优选地具有连续的数字组，连续组中的位数是作为存储器字中的地址位置数和数据位数的函数。存储器数据输入寄存器被配置为循环回路，并添加额外的虚拟位以提供比数据输入寄存器更长的再循环回路。可以在数据输入寄存器中或与多个虚拟寄存器位组合地产生多个独立的循环回路。

5. 发明授权

US4179001A Underground drilling and casing method and apparatus 失效
标题翻译：地下钻井及套管方法及装置
公开(公告)号：US4179001A
公开(公告)日：1979-12-18
申请号：US836219
申请日：1977-09-23
申请人： Norman H. Still , Robert W. Berry, Jr.
发明人： Norman H. Still , Robert W. Berry, Jr.
IPC分类号： E21B7/20 , E21B17/10 , E21D3/00 , E21B19/00
CPC分类号： E21B17/10 , E21B7/20
摘要： In an underground mine, a machine for drilling upwardly is placed in one tunnel of the mine and is used to drill a vertical shaft communicating with another tunnel at a higher elevation. The machine is operated so as to install a liner or casing in the shaft in a step-by-step fashion, substantially concurrently with the corresponding steps of the drilling operation.
摘要翻译：在地下矿井中，向上钻孔的机器放置在矿井的一个隧道内，用于在较高高度与另一个隧道相通的垂直轴钻。操作该机器，以便以一步一步的方式将衬套或套管安装在轴中，基本上与钻孔操作的相应步骤同时进行。

6. 发明授权

US09020779B2 Detecting cross-talk on processor links 有权
标题翻译：检测处理器链路上的串扰
公开(公告)号：US09020779B2
公开(公告)日：2015-04-28
申请号：US13281097
申请日：2011-10-25
申请人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/263 , G06F9/30 , G06F11/34
CPC分类号： G06F9/30145 , G06F9/30 , G06F11/3409 , G06F11/3414 , G06F11/3466 , G06F11/349
摘要： A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.
摘要翻译：多个处理器链路中的第一个处理器链路的多个数据通路中的第一个被确定为对于多个数据通道具有最弱的基本性能测量。经由剩余处理器链路的第一组发送切换数据模式，并且经由剩余处理器链路的第二组发送安静数据模式。如果第一数据线的性能相对于相应的基本性能测量增加，则剩余处理器链路的第一组从剩余处理器链路中消除。如果第一数据通道的性能相对于相应的基本性能测量值降低，则剩余处理器链路的第二组从剩余处理器链路中消除。重复执行上述操作，直到识别出被确定为降低多个数据通道中的第一个数据通道的性能的攻击者处理器链路。

7. 发明授权

US08826092B2 Characterization and validation of processor links 有权
公开(公告)号：US08826092B2
公开(公告)日：2014-09-02
申请号：US13281081
申请日：2011-10-25
申请人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/00 , G01R31/319 , G06F11/22
CPC分类号： G06F11/3089 , G01R31/31926 , G06F9/30 , G06F9/30007 , G06F11/22 , G06F11/221 , G06F11/3409 , G06F11/3414 , G06F11/349 , G06F15/00
摘要： A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

8. 发明授权

US08165847B2 Implementing a programmable DMA master with write inconsistency determination 失效
标题翻译：实现具有写入不一致性确定的可编程DMA主机
公开(公告)号：US08165847B2
公开(公告)日：2012-04-24
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G06F11/30 , G11C29/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

9. 发明申请

US20100250943A1 METHOD FOR SECURITY IN ELECTRONICALLY FUSED ENCRYPTION KEYS 有权
标题翻译：电子加热加压棒的安全方法
公开(公告)号：US20100250943A1
公开(公告)日：2010-09-30
申请号：US12413016
申请日：2009-03-27
申请人： Robert W. Berry, JR. , Jonathan J. DeMent , John S. Liberty
发明人： Robert W. Berry, JR. , Jonathan J. DeMent , John S. Liberty
IPC分类号： H04L9/32 , G06F11/00 , H04L9/06
CPC分类号： H04L9/32 , G06F21/75 , H04L2209/34 , H04L2209/56
摘要： A method for electronically fused encryption key security includes inserting a plurality of inverters between a bank of security fuses and a fuse sense logic module. The method also includes sensing an activated set of the bank of security fuses and the plurality of inverters. The method further includes comparing the sensed activated set of the bank of security fuses and the plurality of inverters with a software key to determine whether at least a substantial match is made.
摘要翻译：一种用于电子融合加密密钥安全性的方法包括在安全保险丝组和熔丝检测逻辑模块之间插入多个逆变器。该方法还包括感测安全熔断器组和多个逆变器的激活组。该方法还包括将感测到的安全熔断器组和多个逆变器的激活组与软件密钥进行比较，以确定是否至少进行了实质的匹配。

10. 发明申请

US20100161921A1 FLASH ROM PROGRAMMING 有权
标题翻译：闪存编程
公开(公告)号：US20100161921A1
公开(公告)日：2010-06-24
申请号：US12339018
申请日：2008-12-18
申请人： Robert W. Berry, JR. , Michael Criscolo , Michael T. Saunders
发明人： Robert W. Berry, JR. , Michael Criscolo , Michael T. Saunders
IPC分类号： G06F13/00
CPC分类号： G11C16/102 , G06F8/66
摘要： A method comprises providing a golden ROM unit comprising known good ROM code. The golden ROM is coupled to a ROM socket of a target system. The target system is booted, wherein booting comprises providing power to the target system and independently providing power to the ROM socket. The known good ROM code is loaded from the golden ROM to a system memory of the target system. Power is removed from the ROM socket and the golden ROM is decoupled from the ROM socket. A first subject ROM is coupled to the ROM socket. Power is provided to the ROM socket and the first subject ROM is programmed with the known good ROM code.
摘要翻译：一种方法包括提供包括已知的良好ROM码的金色ROM单元。金色ROM耦合到目标系统的ROM插槽。引导目标系统，其中引导包括向目标系统提供电力并且独立地向ROM插槽供电。已知的良好ROM代码从金色ROM加载到目标系统的系统内存。电源从ROM插槽中取出，金色ROM从ROM插槽中脱离。第一主题ROM耦合到ROM插槽。电源提供给ROM插槽，第一个对象ROM用已知的良好的ROM代码进行编程。

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