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1. 发明申请

US20100250943A1 METHOD FOR SECURITY IN ELECTRONICALLY FUSED ENCRYPTION KEYS 有权
标题翻译：电子加热加压棒的安全方法
公开(公告)号：US20100250943A1
公开(公告)日：2010-09-30
申请号：US12413016
申请日：2009-03-27
申请人： Robert W. Berry, JR. , Jonathan J. DeMent , John S. Liberty
发明人： Robert W. Berry, JR. , Jonathan J. DeMent , John S. Liberty
IPC分类号： H04L9/32 , G06F11/00 , H04L9/06
CPC分类号： H04L9/32 , G06F21/75 , H04L2209/34 , H04L2209/56
摘要： A method for electronically fused encryption key security includes inserting a plurality of inverters between a bank of security fuses and a fuse sense logic module. The method also includes sensing an activated set of the bank of security fuses and the plurality of inverters. The method further includes comparing the sensed activated set of the bank of security fuses and the plurality of inverters with a software key to determine whether at least a substantial match is made.
摘要翻译：一种用于电子融合加密密钥安全性的方法包括在安全保险丝组和熔丝检测逻辑模块之间插入多个逆变器。该方法还包括感测安全熔断器组和多个逆变器的激活组。该方法还包括将感测到的安全熔断器组和多个逆变器的激活组与软件密钥进行比较，以确定是否至少进行了实质的匹配。

2. 发明授权

US08230495B2 Method for security in electronically fused encryption keys 有权
标题翻译：电子密码加密密钥的安全方法
公开(公告)号：US08230495B2
公开(公告)日：2012-07-24
申请号：US12413016
申请日：2009-03-27
申请人： Robert W. Berry, Jr. , Jonathan J. DeMent , John S. Liberty
发明人： Robert W. Berry, Jr. , Jonathan J. DeMent , John S. Liberty
IPC分类号： G06F21/00
CPC分类号： H04L9/32 , G06F21/75 , H04L2209/34 , H04L2209/56
摘要： A method for electronically fused encryption key security includes inserting a plurality of inverters between a bank of security fuses and a fuse sense logic module. The method also includes sensing an activated set of the bank of security fuses and the plurality of inverters. The method further includes comparing the sensed activated set of the bank of security fuses and the plurality of inverters with a software key to determine whether at least a substantial match is made.
摘要翻译：一种用于电子融合加密密钥安全性的方法包括在安全保险丝组和熔丝检测逻辑模块之间插入多个逆变器。该方法还包括感测安全熔断器组和多个逆变器的激活组。该方法还包括将感测到的安全熔断器组和多个逆变器的激活组与软件密钥进行比较，以确定是否至少进行了实质的匹配。

3. 发明授权

US07930457B2 Channel mechanisms for communicating with a processor event facility 有权
标题翻译：用于与处理器事件设备进行通信的通道机制
公开(公告)号：US07930457B2
公开(公告)日：2011-04-19
申请号：US12361907
申请日：2009-01-29
申请人： Michael N. Day , Charles R. Johns , John S. Liberty , Todd E. Swanson
发明人： Michael N. Day , Charles R. Johns , John S. Liberty , Todd E. Swanson
IPC分类号： G06F3/00 , G06F13/24 , G06F13/32
CPC分类号： G06F13/24
摘要： Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了与处理器事件设施通信的机制。这些机制使用通道接口作为与处理器事件设施通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

4. 发明申请

US20100161848A1 Programmable Direct Memory Access Engine 有权
标题翻译：可编程直接存储器访问引擎
公开(公告)号：US20100161848A1
公开(公告)日：2010-06-24
申请号：US12342280
申请日：2008-12-23
申请人： Brian K. Flachs , Charles R. Johns , John S. Liberty , Brad W. Michael
发明人： Brian K. Flachs , Charles R. Johns , John S. Liberty , Brad W. Michael
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A mechanism for programming a direct memory access engine operating as a single thread processor is provided. A program is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the program located in the local memory is to be executed. The direct memory access engine executes the program without intervention by a host processor. Responsive to the program completing execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.
摘要翻译：提供了一种用于对作为单线程处理器操作的直接存储器访问引擎进行编程的机制。从与直接存储器访问引擎相关联的本地存储器中的主处理器接收程序。在来自主处理器的直接存储器访问引擎中接收到指示将要执行位于本地存储器中的程序的请求。直接存储器访问引擎在没有主机处理器干预的情况下执行程序。响应程序完成执行，直接存储器访问引擎向主处理器发送指示程序已经完成执行的完成通知。

5. 发明授权

US08918442B2 Reducing bias in hardware generated random numbers 有权
公开(公告)号：US08918442B2
公开(公告)日：2014-12-23
申请号：US13592295
申请日：2012-08-22
申请人： John S. Liberty , Marty L. Tsai
发明人： John S. Liberty , Marty L. Tsai
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/58 , G06F7/588
摘要： A random number generator of a processor comprises a whitener for reducing the bias in random numbers generated by the random number generator. The whitener receives a random number of a first length read by an array of latches with inputs from an array of oscillators. The whitener dynamically creates a mask of the first length based on a parity of at least one previous random number read from the array of latches during at least one cycle prior to reading the random number. The whitener applies a compare operation between the random number and the mask to generate a whitened random number of the first length, with reduced bias, without reducing randomness.

6. 发明申请

US20140059099A1 REDUCING BIAS IN HARDWARE GENERATED RANDOM NUMBERS 有权
标题翻译：减少硬件生成随机数的偏差
公开(公告)号：US20140059099A1
公开(公告)日：2014-02-27
申请号：US13592295
申请日：2012-08-22
申请人： John S. Liberty , Marty L. Tsai
发明人： John S. Liberty , Marty L. Tsai
IPC分类号： G06F7/58
CPC分类号： G06F7/58 , G06F7/588
摘要： A random number generator of a processor comprises a whitener for reducing the bias in random numbers generated by the random number generator. The whitener receives a random number of a first length read by an array of latches with inputs from an array of oscillators. The whitener dynamically creates a mask of the first length based on a parity of at least one previous random number read from the array of latches during at least one cycle prior to reading the random number. The whitener applies a compare operation between the random number and the mask to generate a whitened random number of the first length, with reduced bias, without reducing randomness.
摘要翻译：处理器的随机数发生器包括用于减少由随机数发生器产生的随机数的偏差的增白器。增白器接收由具有来自振荡器阵列的输入的锁存器阵列读取的第一长度的随机数。基于在读取随机数之前的至少一个周期期间从锁存器阵列读取的至少一个先前随机数的奇偶性，动态地创建第一长度的掩码。增白剂在随机数和掩模之间应用比较操作，以减少偏差产生第一长度的白化随机数，而不减少随机性。

7. 发明申请

US20100161846A1 Multithreaded Programmable Direct Memory Access Engine 有权
标题翻译：多线程可编程直接存储器访问引擎
公开(公告)号：US20100161846A1
公开(公告)日：2010-06-24
申请号：US12342501
申请日：2008-12-23
申请人： Brian K. Flachs , Harm P. Hofstee , Charles R. Johns , Matthew E. King , John S. Liberty , Brad W. Michael
发明人： Brian K. Flachs , Harm P. Hofstee , Charles R. Johns , Matthew E. King , John S. Liberty , Brad W. Michael
IPC分类号： G06F3/00
CPC分类号： G06F9/30087 , G06F9/3877 , G06F13/1663 , G06F13/28
摘要： A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.
摘要翻译：提供了编程作为多线程处理器操作的直接存储器访问引擎的机制。从与直接存储器访问引擎相关联的本地存储器中的主机处理器接收多个程序。在来自主机处理器的直接存储器访问引擎中接收到指示将要执行位于本地存储器中的多个程序的请求。直接存储器访问引擎在主机处理器的干预下执行多个程序中的两个或多个。当多个程序中的两个或更多个程序中的每一个完成执行时，直接存储器访问引擎向主处理器发送指示程序已经完成执行的完成通知。

8. 发明申请

US20120246354A1 Multithreaded Programmable Direct Memory Access Engine 有权
标题翻译：多线程可编程直接存储器访问引擎
公开(公告)号：US20120246354A1
公开(公告)日：2012-09-27
申请号：US13488856
申请日：2012-06-05
申请人： Brian K. Flachs , Harm P. Hofstee , Charles R. Johns , Matthew E. King , John S. Liberty , Brad W. Michael
发明人： Brian K. Flachs , Harm P. Hofstee , Charles R. Johns , Matthew E. King , John S. Liberty , Brad W. Michael
IPC分类号： G06F13/28
CPC分类号： G06F9/30087 , G06F9/3877 , G06F13/1663 , G06F13/28
摘要： A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.
摘要翻译：提供了编程作为多线程处理器操作的直接存储器访问引擎的机制。从与直接存储器访问引擎相关联的本地存储器中的主机处理器接收多个程序。在来自主机处理器的直接存储器访问引擎中接收到指示将要执行位于本地存储器中的多个程序的请求。直接存储器访问引擎在主机处理器的干预下执行多个程序中的两个或多个。当多个程序中的两个或更多个程序中的每一个完成执行时，直接存储器访问引擎向主处理器发送指示程序已经完成执行的完成通知。

9. 发明授权

US07778271B2 Method for communicating instructions and data between a processor and external devices 失效
标题翻译：在处理器和外部设备之间传送指令和数据的方法
公开(公告)号：US07778271B2
公开(公告)日：2010-08-17
申请号：US11207970
申请日：2005-08-19
申请人： Michael N. Day , Charles R. Johns , John S. Liberty , Todd E. Swanson , Thuong Q. Truong
发明人： Michael N. Day , Charles R. Johns , John S. Liberty , Todd E. Swanson , Thuong Q. Truong
IPC分类号： H04J3/00 , G06F3/00 , G06F9/00
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和外部设备之间传送指令和数据的方法。该方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

10. 发明申请

US20090070654A1 Design Structure For A Processor System With Background Error Handling Feature 审中-公开
标题翻译：具有背景错误处理功能的处理器系统的设计结构
公开(公告)号：US20090070654A1
公开(公告)日：2009-03-12
申请号：US12272812
申请日：2008-11-18
申请人： Brian Flachs , H. Peter Hofstee , John S. Liberty , Brad W. Michael
发明人： Brian Flachs , H. Peter Hofstee , John S. Liberty , Brad W. Michael
IPC分类号： G11C29/52 , G06F11/10 , H03M13/05
CPC分类号： H03M13/19 , G06F11/1044 , H03M13/09
摘要： A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor system that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. The design structure may specify ECC hardware circuitry that provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The design structure for the processor system may permit the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The design structure may provide for local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.
摘要翻译：用于处理器系统的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。该设计结构可以包括在存储器管理电路内集成纠错码（ECC）检测和校正硬件的处理器系统。设计结构可以指定ECC硬件电路，其提供与存储器数据读取和写入相结合的ECC数据位的检测，校正和生成。处理器系统的设计结构可以允许检测和校正从本地存储器在线读取的软单位错误，同时使用读修改写DMA电路逻辑来校正本地存储器数据。设计结构可以在后台存储器擦除过程中提供本地存储器数据错误检测和校正，而不需要附加的在线数据逻辑。

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