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1. 发明授权

US06598216B2 Method for enhancing a power bus in I/O regions of an ASIC device 失效
标题翻译：用于增强ASIC设备的I / O区域中的电力总线的方法
公开(公告)号：US06598216B2
公开(公告)日：2003-07-22
申请号：US09924673
申请日：2001-08-08
申请人： Francis Chan , Charles S. Chiu , Robert Charles Cusimano , Donald S. Kent , Gulsun Yasar
发明人： Francis Chan , Charles S. Chiu , Robert Charles Cusimano , Donald S. Kent , Gulsun Yasar
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A method for enhancing power bus for I/O libraries in ASIC designs is disclosed. An I/O assignment for I/O circuits to be utilized in an ASIC design is initially generated. Each I/O circuit may obtain power from either a primary I/O power bus or a secondary I/O power bus. A determination is then made as to whether or not the I/O assignment meets certain predetermined power distribution requirements. In a determination that the I/O assignment does not meet the predetermined power bus distribution requirements, a power enhancement cell is added. The power enhancement circuit includes at least one metal line for connecting the primary I/O power bus to the secondary I/O power bus in order for the I/O assignment to meet the power bus distribution requirements.
摘要翻译：公开了一种用于增强ASIC设计中的I / O库的电源总线的方法。最初生成用于ASIC设计中的I / O电路的I / O分配。每个I / O电路可以从主I / O电源总线或辅助I / O电源总线获得电源。然后确定I / O分配是否满足某些预定的功率分配要求。在确定I / O分配不满足预定功率总线分配要求的情况下，增加功率增强单元。功率增强电路包括用于将主I / O电源总线连接到辅助I / O电源总线的至少一个金属线，以便I / O分配满足电力总线分配要求。

2. 发明授权

US5375091A Method and apparatus for memory dynamic burn-in and test 失效
标题翻译：用于记忆动态老化和测试的方法和装置
公开(公告)号：US5375091A
公开(公告)日：1994-12-20
申请号：US163803
申请日：1993-12-08
申请人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
发明人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
IPC分类号： G11C29/10 , G11C29/50 , G11C13/00
CPC分类号： G11C29/10 , G11C29/50
摘要： A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.
摘要翻译：嵌入在集成处理器芯片中的存储器通过重复地将测试图案写入存储器的数据位置而被动态地受到压力测试，其中高百分比的存储器单元被顺序地写有补充数据，以便在存储器上产生高应力设备。作为存储器的地址位置的数量和存储器数据字的数据位的数量的函数产生测试图案。每次存储器寻址时，测试模式都会旋转。测试图案优选地具有连续的数字组，连续组中的位数是作为存储器字中的地址位置数和数据位数的函数。存储器数据输入寄存器被配置为循环回路，并添加额外的虚拟位以提供比数据输入寄存器更长的再循环回路。可以在数据输入寄存器中或与多个虚拟寄存器位组合地产生多个独立的循环回路。

3. 发明授权

US5761078A Field programmable gate arrays using semi-hard multicell macros 失效
标题翻译：使用半硬多核宏的现场可编程门阵列
公开(公告)号：US5761078A
公开(公告)日：1998-06-02
申请号：US618060
申请日：1996-03-21
申请人： Christine Marie Fuller , Scott Whitney Gould , Steven Paul Hartman , Eric Ernest Millham , Gulsun Yasar
发明人： Christine Marie Fuller , Scott Whitney Gould , Steven Paul Hartman , Eric Ernest Millham , Gulsun Yasar
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer implemented method for the automated placement and routing in the design of field programmable gate arrays achieves optimal timing. In a library of primitives and macros from which a designer may choose to implement a given circuit design, at least some of said macros are "semi-hard" macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement. A logical netlist containing references to macros and how to connect them together to perform a logical function is first created. The logical netlist is then translated to a physical netlist using a mapper function. This physical netlist for the semi-hard macros specifies what is to be connected but not how. The best place to put each macro on the field programmable gate array is found using a placer function. The placer function thus determines an absolute position of the macros. Pre-defined macro direct connections are routed using a router function. The router function determines an optimal path to connect the semi-hard macros. Finally, a bitstream is generated from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.
摘要翻译：用于现场可编程门阵列设计中的自动放置和布线的计算机实现方法实现了最佳的定时。在设计者可以选择实现给定电路设计的原语和宏的库中，至少一些所述宏是“半硬”宏，其中指定了直接连接和相对放置，同时以某种方式请求本地总线路由这不会限制宏放置。首先创建包含对宏的引用以及如何将它们连接在一起以执行逻辑功能的逻辑网表。然后使用映射器函数将逻辑网表转换为物理网表。这个半硬宏的物理网表指定了要连接的内容，但不是如何。使用放置功能可以找到将每个宏放在现场可编程门阵列上的最佳位置。因此，放置函数决定宏的绝对位置。使用路由器功能路由预定义的宏直连。路由器功能确定连接半硬宏的最佳路径。最后，由放置器和路由器开发的放置和路由信息生成比特流，以对现场可编程门阵列进行编程以执行网表逻辑功能。

4. 发明授权

US06584606B1 Fast method of I/O circuit placement and electrical rule checking 失效
标题翻译：快速的I / O电路放置方法和电气规则检查
公开(公告)号：US06584606B1
公开(公告)日：2003-06-24
申请号：US09584416
申请日：2000-06-01
申请人： Charles S. Chiu , James P. Libous , Rory D. Loughran , Joseph Natonio , Robert A. Proctor , Gulsun Yasar
发明人： Charles S. Chiu , James P. Libous , Rory D. Loughran , Joseph Natonio , Robert A. Proctor , Gulsun Yasar
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.
摘要翻译：分析集成电路（例如ASIC）的I / O单元布局的方法包括在所选择的芯片图像上定义所提出的I / O单元布局，为电迁移，IR电压降和di / dt噪声提供一组限制规则所选择的芯片图像，为所提出的I / O单元布局中使用的每个I / O单元类型提供特征，通过对所提出的I / O单元布局应用限制规则来检查所提出的I / O单元布局，并报告所有I / 在所提出的I / O单元布局中使用的O单元不符合所选芯片图像的限制规则。

5. 发明授权

US06499134B1 Method of assigning integrated circuit I/O signals in an integrated circuit package 有权
标题翻译：在集成电路封装中分配集成电路I / O信号的方法
公开(公告)号：US06499134B1
公开(公告)日：2002-12-24
申请号：US09615149
申请日：2000-07-13
申请人： Patrick H. Buffet , Paul E. Dunn , Joseph Natonio , Robert A. Proctor , Gulsun Yasar
发明人： Patrick H. Buffet , Paul E. Dunn , Joseph Natonio , Robert A. Proctor , Gulsun Yasar
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for improving the crosstalk and time-of-flight performance for signals in an integrated circuit with respect to the package-related wiring. I/O pads in the package-related wiring of a logic design meeting specified crosstalk and time-of-flight constraints are identified using a software tool. The tool produces a graphical display in which the identified I/O pads are highlighted. The tool enables a user to graphically manipulate the display to assign, i.e., establish an electrical connection, between I/O circuits corresponding to the signals and the highlighted I/O pads.
摘要翻译：一种用于改善集成电路中针对封装相关布线的信号的串扰和飞行时间性能的方法。使用软件工具识别逻辑设计会议规定的串扰和飞行时间限制的封装相关布线中的I / O焊盘。该工具产生图形显示，其中识别的I / O焊盘被突出显示。该工具使得用户能够以图形方式操纵显示器，以分配对应于信号的I / O电路和突出显示的I / O焊盘之间的电连接。

6. 发明授权

US5633877A Programmable built-in self test method and controller for arrays 失效
标题翻译：可编程内置自检方法和阵列控制器
公开(公告)号：US5633877A
公开(公告)日：1997-05-27
申请号：US450585
申请日：1995-05-31
申请人： Philip G. Shephard, III , William V. Huott , Paul R. Turgeon , Robert W. Berry, Jr. , Gulsun Yasar , Frederick J. Cox , Pradip Patel , Joseph B. Hanley, III
发明人： Philip G. Shephard, III , William V. Huott , Paul R. Turgeon , Robert W. Berry, Jr. , Gulsun Yasar , Frederick J. Cox , Pradip Patel , Joseph B. Hanley, III
IPC分类号： G06F11/22 , G06F11/267 , G06F11/273 , G11C29/00 , G11C29/10 , G11C29/16 , G11C29/32 , G06F11/00
CPC分类号： G11C29/789 , G01R31/318385 , G06F11/22 , G06F11/2236 , G06F11/2294 , G11C29/16 , G11C29/10 , G11C29/32
摘要： An array built-in self test system has a scannable memory elements and a controller which, in combination, allow self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy.
摘要翻译：阵列内置的自检系统具有可扫描的存储器元件和控制器，其组合地允许在不对测试逻辑进行硬件改变的情况下修改自检功能（例如测试模式，读/写访问和测试序列）。测试顺序由逻辑测试向量控制，可以改变，使得开发复杂测试序列的任务比较容易。

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