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1. 发明授权

US09020779B2 Detecting cross-talk on processor links 有权
标题翻译：检测处理器链路上的串扰
公开(公告)号：US09020779B2
公开(公告)日：2015-04-28
申请号：US13281097
申请日：2011-10-25
申请人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/263 , G06F9/30 , G06F11/34
CPC分类号： G06F9/30145 , G06F9/30 , G06F11/3409 , G06F11/3414 , G06F11/3466 , G06F11/349
摘要： A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.
摘要翻译：多个处理器链路中的第一个处理器链路的多个数据通路中的第一个被确定为对于多个数据通道具有最弱的基本性能测量。经由剩余处理器链路的第一组发送切换数据模式，并且经由剩余处理器链路的第二组发送安静数据模式。如果第一数据线的性能相对于相应的基本性能测量增加，则剩余处理器链路的第一组从剩余处理器链路中消除。如果第一数据通道的性能相对于相应的基本性能测量值降低，则剩余处理器链路的第二组从剩余处理器链路中消除。重复执行上述操作，直到识别出被确定为降低多个数据通道中的第一个数据通道的性能的攻击者处理器链路。

2. 发明授权

US08826092B2 Characterization and validation of processor links 有权
公开(公告)号：US08826092B2
公开(公告)日：2014-09-02
申请号：US13281081
申请日：2011-10-25
申请人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/00 , G01R31/319 , G06F11/22
CPC分类号： G06F11/3089 , G01R31/31926 , G06F9/30 , G06F9/30007 , G06F11/22 , G06F11/221 , G06F11/3409 , G06F11/3414 , G06F11/349 , G06F15/00
摘要： A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

3. 发明申请

US20120330616A1 FREQUENCY GUARD BAND VALIDATION OF PROCESSORS 有权
标题翻译：加工商的频率防护带验证
公开(公告)号：US20120330616A1
公开(公告)日：2012-12-27
申请号：US13170150
申请日：2011-06-27
申请人： Robert W. Berry , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
发明人： Robert W. Berry , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
IPC分类号： G06F11/30
CPC分类号： G01R31/2879 , G06F11/24
摘要： A frequency guard band validation unit can determine whether at least one of a plurality of previously validated processors was validated on a first system having a substantially similar configuration as a second system in which an unvalidated processor is being tested. If at least one of the plurality of previously validated processors was validated on the first system, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency. This can reduce the overall validation cycle time.
摘要翻译：频率保护频带验证单元可以确定在具有基本相似配置的第一系统上验证多个先前验证的处理器中的至少一个是否是正在测试未验证的处理器的第二系统。如果多个先前验证的处理器中的至少一个在第一系统上被验证，则可以至少部分地基于与先前多个先前验证的处理器的子集相关联的系统参数数据来计算与未验证的处理器相关联的验证开始频率在第一个系统上验证的经过验证的处理器。否则，至少部分地基于与未经验证的处理器相关联的测试仪参数数据来计算与未验证的处理器相关联的验证开始频率。无效处理器的保护频带频率的验证在验证开始频率处启动。这可以减少总体验证周期时间。

4. 发明授权

US09128887B2 Using a buffer to replace failed memory cells in a memory component 有权
标题翻译：使用缓冲区来替换内存组件中的故障内存单元
公开(公告)号：US09128887B2
公开(公告)日：2015-09-08
申请号：US13589487
申请日：2012-08-20
申请人： Manoj Dusanapudi , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj , Saravanan Sethuraman , Diyanesh B. Vidyapoornachary
发明人： Manoj Dusanapudi , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj , Saravanan Sethuraman , Diyanesh B. Vidyapoornachary
IPC分类号： G06F11/16
CPC分类号： G06F11/16 , G06F11/1666 , G06F11/20
摘要： Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.
摘要翻译：提供了用于使用缓冲器来替换存储器组件中的故障存储器单元的方法和数据处理系统。实施例包括确定存储在存储器组件的多个存储器单元内的数据的第一副本包含一个或多个错误; 响应于确定所述第一副本包含一个或多个错误，确定所述缓冲器内的备份高速缓存是否包含所述数据的第二副本; 并且响应于确定所述备份高速缓存包含所述数据的所述第二副本，将所述第二副本从所述备份高速缓存传送到所述缓冲器内的错误数据队列（EDQ）内的位置，并更新所述缓冲器控制器以使用所述缓冲器控制器内的位置 EDQ而不是存储器组件内的多个存储器单元。

5. 发明授权

US08855969B2 Frequency guard band validation of processors 有权
标题翻译：处理器的频率保护带验证
公开(公告)号：US08855969B2
公开(公告)日：2014-10-07
申请号：US13170150
申请日：2011-06-27
申请人： Robert W. Berry, Jr. , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
发明人： Robert W. Berry, Jr. , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
IPC分类号： G01R31/28 , G06F11/24
CPC分类号： G01R31/2879 , G06F11/24
摘要： Whether validation of at least one of a plurality of previously validated processors on a first system produced data usable for computing a validation start frequency of an unvalidated processor on a second system is determined. If validation of at least one of the plurality of previously validated processors on the first system produced data usable for validating the unvalidated processor, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency.
摘要翻译：确定第一系统上的多个先前验证的处理器中的至少一个的验证是否产生可用于计算第二系统上未经验证的处理器的验证开始频率的数据。如果对第一系统上的多个先前验证的处理器中的至少一个的验证产生可用于验证未验证的处理器的数据，则可以至少部分地基于与系统参数数据相关联地计算与未验证的处理器相关联的验证开始频率具有在第一系统上验证的多个先前验证的处理器的子集。否则，至少部分地基于与未经验证的处理器相关联的测试仪参数数据来计算与未验证的处理器相关联的验证开始频率。无效处理器的保护频带频率的验证在验证开始频率处启动。

6. 发明申请

US20140053016A1 Using A Buffer To Replace Failed Memory Cells In A Memory Component 有权
标题翻译：使用缓冲区替换存储器组件中的故障存储单元
公开(公告)号：US20140053016A1
公开(公告)日：2014-02-20
申请号：US13589487
申请日：2012-08-20
申请人： Manoj Dusanapudi , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj , Saravanan Sethuraman , Diyanesh B. Vidyapoornachary
发明人： Manoj Dusanapudi , Prasanna Jayaraman , Anil B. Lingambudi , Girisankar Paulraj , Saravanan Sethuraman , Diyanesh B. Vidyapoornachary
IPC分类号： G06F11/16
CPC分类号： G06F11/16 , G06F11/1666 , G06F11/20
摘要： Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.
摘要翻译：提供了用于使用缓冲器来替换存储器组件中的故障存储器单元的方法和数据处理系统。实施例包括确定存储在存储器组件的多个存储器单元内的数据的第一副本包含一个或多个错误; 响应于确定所述第一副本包含一个或多个错误，确定所述缓冲器内的备份高速缓存是否包含所述数据的第二副本; 并且响应于确定所述备份高速缓存包含所述数据的所述第二副本，将所述第二副本从所述备份高速缓存传送到所述缓冲器内的错误数据队列（EDQ）内的位置，并更新所述缓冲器控制器以使用所述缓冲器控制器内的位置 EDQ而不是存储器组件内的多个存储器单元。

7. 发明申请

US20130103927A1 CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS 有权
标题翻译：处理器链接的特征和验证
公开(公告)号：US20130103927A1
公开(公告)日：2013-04-25
申请号：US13281081
申请日：2011-10-25
申请人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F15/00 , G06F9/30
CPC分类号： G06F11/3089 , G01R31/31926 , G06F9/30 , G06F9/30007 , G06F11/22 , G06F11/221 , G06F11/3409 , G06F11/3414 , G06F11/349 , G06F15/00
摘要： A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.
摘要翻译：选择耦合第一处理器和第二处理器的处理器链接用于验证，并且识别与第一处理器和第二处理器相关联的多个通信参数设置。第一和第二处理器依次配置有每个通信参数设置。根据通信参数设置，从第一处理器向第二处理器提供一个或多个测试数据模式。至少部分地基于在第二处理器处接收到的测试数据模式来确定与所选择的处理器链路和通信参数设置相关联的性能测量。选择与最高性能测量值相关联的通信参数设置之一。所选择的通信参数设置被应用于第一和第二处理器，用于经由处理器链路在第一和第二处理器之间进行后续通信。

8. 发明申请

US20130103354A1 DETECTING CROSS-TALK ON PROCESSOR LINKS 有权
标题翻译：检测处理器链接的交叉口
公开(公告)号：US20130103354A1
公开(公告)日：2013-04-25
申请号：US13281097
申请日：2011-10-25
申请人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/30
CPC分类号： G06F9/30145 , G06F9/30 , G06F11/3409 , G06F11/3414 , G06F11/3466 , G06F11/349
摘要： A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.
摘要翻译：多个处理器链路中的第一个处理器链路的多个数据通路中的第一个被确定为对于多个数据通道具有最弱的基本性能测量。经由剩余处理器链路的第一组发送切换数据模式，并且经由剩余处理器链路的第二组发送安静数据模式。如果第一数据线的性能相对于相应的基本性能测量增加，则剩余处理器链路的第一组从剩余处理器链路中消除。如果第一数据通道的性能相对于相应的基本性能测量值降低，则剩余处理器链路的第二组从剩余处理器链路中消除。重复执行上述操作，直到识别出被确定为降低多个数据通道中的第一个数据通道的性能的攻击者处理器链路。

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