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1. 发明授权

US09064712B2 Monolithic microwave integrated circuit 有权
标题翻译：单片微波集成电路
公开(公告)号：US09064712B2
公开(公告)日：2015-06-23
申请号：US12855479
申请日：2010-08-12
申请人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
发明人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
IPC分类号： H01L23/522 , H01L27/06 , H01L23/48 , H01L23/66 , H03F3/195 , H01L23/00
CPC分类号： H01L23/66 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L27/0617 , H01L27/0629 , H01L27/0727 , H01L28/10 , H01L28/40 , H01L29/7816 , H01L2223/6616 , H01L2223/6655 , H01L2223/6683 , H01L2224/48091 , H01L2224/49175 , H01L2225/06541 , H01L2924/00014 , H01L2924/12044 , H01L2924/13062 , H01L2924/14 , H01L2924/1423 , H01L2924/30107 , H03F3/195 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.
摘要翻译：使用高电阻率（例如≥100欧姆 - 厘米）的半导体衬底（60）和较低电阻电感（44'，45'）可以避免或减轻以微波频率操作时与单片集成电路（IC）的无源部件相关的低Q，）用于IC（46）。这消除了覆盖衬底（60）的平面电感器（44,45）和互连（50-1'，52-1'，94,94'，94“）的显着的衬底内电磁耦合损耗。有源晶体管（41'）在靠近前表面（63）的基底（60）中形成。平面电容器（42'，43'）也形成在衬底（60）的前表面（63）上方。晶体管的各个端子（42-1'，42-2'，43-1,43-2'，50'，51'，52'，42-1'，42-2'等）（41'），电容器（42'，43'）和电感器（44'，45'）耦合到衬底（60）的背面（62）上的接地平面（69）使用贯通衬底通孔（98,98'）来最小化寄生电阻。通过将平面电感器（44'，45'）和大电流承载导体（52-1'）相关联的寄生电阻放置在IC的外表面上，使其可以被制成基本上更厚且电阻更低。其结果是先前无法获得的单片微波IC（46,58）。

2. 发明授权

US08628781B2 Prevention and treatment of cast nephropathy 有权
标题翻译：预防和治疗流产肾病
公开(公告)号：US08628781B2
公开(公告)日：2014-01-14
申请号：US13639002
申请日：2011-04-01
申请人： Paul W. Sanders
发明人： Paul W. Sanders
IPC分类号： A61K39/00 , A61K38/00 , A61K38/10 , A61K38/12 , A61K38/04
CPC分类号： C07K7/08 , A61K38/00 , C07K14/47 , C07K16/4241 , C07K2317/515 , C07K2317/565 , C12N15/113 , C12N2310/11 , C12N2310/14
摘要： Provided herein are polypeptides comprising or consisting essentially of a QSYDNTLSGSYVF (SEQ ID NO:1) or LSADSSGSYLYVF (SEQ ID NO:2) amino acid sequence. Also provided herein are methods of treating or preventing cast nephropathy in a subject. The methods comprise identifying a subject with or at risk of developing cast nephropathy and administering to the subject any of the polypeptides disclosed herein.
摘要翻译：本文提供的是包含或基本上由QSYDNTLSGSYVF（SEQ ID NO：1）或LSADSSGSYLYVF（SEQ ID NO：2）氨基酸序列组成的多肽。本文还提供了治疗或预防受试者中的肾性肾病的方法。所述方法包括鉴定患有或具有发展为流产性肾病的风险的受试者，并向受试者施用本文公开的任何多肽。

3. 发明授权

US08518764B2 Semiconductor structure having a through substrate via (TSV) and method for forming 有权
标题翻译：具有贯通基板通孔（TSV）的半导体结构及其形成方法
公开(公告)号：US08518764B2
公开(公告)日：2013-08-27
申请号：US13279776
申请日：2011-10-24
申请人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
发明人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L21/76898 , H01L21/26586 , H01L23/5227 , H01L23/66 , H01L28/10 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/7835 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.
摘要翻译：半导体器件结构包括具有第一浓度和第一导电类型的背景掺杂的衬底。贯穿基板通孔（TSV）通过基板。器件在衬底的第一侧上具有第二导电性的第一掺杂区域。第二掺杂区域在TSV周围。第二掺杂区具有大于第一浓度的第二浓度的掺杂并且是第一导电类型。

4. 发明授权

US07803714B2 Semiconductor through silicon vias of variable size and method of formation 有权
标题翻译：半导体通过可变尺寸的硅通孔和形成方法
公开(公告)号：US07803714B2
公开(公告)日：2010-09-28
申请号：US12059123
申请日：2008-03-31
申请人： Chandrasekaram Ramiah , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Paul W. Sanders
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3065 , H01L21/76816 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.
摘要翻译：通过提供具有形成在其上的第一导电捕获垫和第二导电捕获垫的衬底来形成穿硅通孔结构。衬底被固定到晶片载体上。第一类型的第一蚀刻在第一和第二导电捕捉垫下面的衬底上进行，以形成第一部分通过衬底通孔，第一直径位于第一导电捕获垫下面，第二部分通过衬底通过下面的与第一直径不同的第二直径的第二导电捕获垫。执行与第一类型不同的第二类型的第二蚀刻，以继续蚀刻第一部分通过基板以分别形成相同深度的第一和第二贯穿基板通孔到第一和第二导电捕捉垫。

5. 发明申请

US20100127394A1 THROUGH SUBSTRATE VIAS FOR BACK-SIDE INTERCONNECTIONS ON VERY THIN SEMICONDUCTOR WAFERS 有权
标题翻译：通过基板VIAS在非常薄的半导体波形上进行背面互连
公开(公告)号：US20100127394A1
公开(公告)日：2010-05-27
申请号：US12277512
申请日：2008-11-25
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L23/528 , H01L21/768 , H01L23/532
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18′); etching (104) via cavities (29) partly through the wafer (18′) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18′) with its front side (35) facing a support structure (40); thinning (107) the wafer (18′) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.) of the filled vias; removing (109) the support structure (40) and separating the individual device or IC assemblies (48) so as to be available for mounting (110) on a further circuit board, tape or larger circuit (50).
摘要翻译：通过以下方式提供通过用于在非常薄的半导体晶片上进行背面电气和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在前表面（19）上形成具有触点（22）的期望的器件区域（21）的最初相对较厚的晶片（18'）; 通过腔（29）在期望的位置部分地通过晶片（18'）蚀刻（104）; 通过耦合到一些设备区域触点（22）的导电材料（32）填充（105）所述通孔腔（29）; 安装（106）所述晶片（18'），其前侧（35）面向支撑结构（40）; 从背面（181）将晶片（18'）变薄（107）（107），以暴露导电材料填充的通孔（321,322,323,324等）的内端（3210,3220,3230，3240等））; 施加（108）耦合到所述填充通孔的暴露端（3210,3220,3230,3240等）的任何期望的背面互连区域（44）; 移除（109）支撑结构（40）并分离各个装置或IC组件（48），以便可用于将另一电路板，带或更大的电路（50）安装（110）。

6. 发明授权

US5338397A Method of forming a semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US5338397A
公开(公告)日：1994-08-16
申请号：US130482
申请日：1993-10-01
申请人： Paul W. Sanders
发明人： Paul W. Sanders
IPC分类号： H01L21/027 , G03F7/20 , H01L21/768 , H01L21/306 , B44C1/22 , C23F1/00
CPC分类号： H01L21/76838 , G03F7/2024 , Y10S438/949
摘要： The present invention provides a method of forming a semiconductor device. A layer of photoresist is applied to a semiconductor wafer. A first mask is used to protect a first portion of the photoresist while a second portion of the photoresist is exposed. A second mask is used to expose a third portion of the photoresist wherein the third portion of the photoresist includes part of the first portion of the photoresist. The photoresist is developed to form a photoresist mask.
摘要翻译：本发明提供一种形成半导体器件的方法。将一层光致抗蚀剂施加到半导体晶片。第一掩模用于保护光致抗蚀剂的第一部分，同时曝光光致抗蚀剂的第二部分。第二掩模用于曝光光致抗蚀剂的第三部分，其中光致抗蚀剂的第三部分包括光致抗蚀剂的第一部分的一部分。将光致抗蚀剂显影以形成光致抗蚀剂掩模。

7. 发明授权

US5273940A Multiple chip package with thinned semiconductor chips 失效
标题翻译：具有薄型半导体芯片的多芯片封装
公开(公告)号：US5273940A
公开(公告)日：1993-12-28
申请号：US898646
申请日：1992-06-15
申请人： Paul W. Sanders
发明人： Paul W. Sanders
IPC分类号： H01L21/60 , H01L23/36 , H01L23/485 , H01L25/065
CPC分类号： H01L24/10 , H01L23/36 , H01L24/13 , H01L24/81 , H01L25/0655 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/81801 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/12044 , H01L2924/30107 , Y10S438/977
摘要： An assembly is formed by coupling a plurality of semiconductor chips (26-29) to a surface of a substrate (17). An encapsulation material (22) is placed on the surface of the substrate (17) to protect the semiconductor chips (26-29) from an external environment. Material is removed from the plurality of semiconductor chips (26-29) to thin each semiconductor chip (26-29) to promote thermal conductivity.
摘要翻译：通过将多个半导体芯片（26-29）耦合到衬底（17）的表面来形成组件。封装材料（22）被放置在衬底（17）的表面上，以保护半导体芯片（26-29）免受外部环境的影响。从多个半导体芯片（26-29）去除材料以使每个半导体芯片（26-29）薄，以促进导热性。

8. 发明授权

US5145795A Semiconductor device and method therefore 失效
标题翻译：半导体器件及其方法
公开(公告)号：US5145795A
公开(公告)日：1992-09-08
申请号：US543233
申请日：1990-06-25
申请人： Paul W. Sanders , Bernard W. Boland
发明人： Paul W. Sanders , Bernard W. Boland
IPC分类号： H01L21/762
CPC分类号： H01L21/76297 , H01L2224/48091 , H01L2224/73265 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , Y10S148/168 , Y10S438/977
摘要： An improved high frequency dielectrically isolated (DIC) transistor (100) or integrated circuit is obtained by providing a highly doped single crystal semiconductor region (112) coupled to the device reference terminal (16') and extending between front (98) and rear (61) faces of the semiconductor die. This allows the reference terminal (16', 116) to be coupled to the package ground plane without use of wire bonds, thereby lowering the common mode impedance. The desired structure is formed in connection with DIC devices (100) by etching first (66) and second (77) nested cavities into a single crystal substrate (60). The cavities (66) form protruding islands (821, 822) of single crystal semiconductor having a height (80+68) about equal the final die thickness (110) and which, after conventional DIC processing using an oxide isolation layer (86) and a poly handle (88), are exposed by grinding away the poly handle (88) to expose the highly doped, single crystal reference terminal feed-through (112).
摘要翻译：通过提供耦合到器件参考端子（16'）并在前面（98）和后面（98）之间延伸的高掺杂单晶半导体区域（112），获得改进的高频介电隔离（DIC）晶体管（100）或集成电路 61）面。这允许参考端子（16'，116）在不使用引线接合的情况下耦合到封装接地层，从而降低共模阻抗。通过将第一（66）和第二（77）嵌套空穴蚀刻到单晶衬底（60）中，与DIC器件（100）相关地形成期望的结构。空腔（66）形成高度（80 + 68）的大约等于最终管芯厚度（110）的单晶半导体的突出岛（821,822），并且在使用氧化物隔离层（86）的常规DIC处理和通过研磨多晶硅手柄（88）以暴露高度掺杂的单晶参考端子馈通（112）来暴露多晶硅手柄（88）。

9. 发明申请

US20130099312A1 SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING 有权
标题翻译：具有通过（TSV）的基底的半导体结构和形成方法
公开(公告)号：US20130099312A1
公开(公告)日：2013-04-25
申请号：US13279776
申请日：2011-10-24
申请人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
发明人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
IPC分类号： H01L29/78 , H01L21/225
CPC分类号： H01L21/76898 , H01L21/26586 , H01L23/5227 , H01L23/66 , H01L28/10 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/7835 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.
摘要翻译：半导体器件结构包括具有第一浓度和第一导电类型的背景掺杂的衬底。贯穿基板通孔（TSV）通过基板。器件在衬底的第一侧上具有第二导电性的第一掺杂区域。第二掺杂区域在TSV周围。第二掺杂区具有大于第一浓度的第二浓度的掺杂并且是第一导电类型。

10. 发明授权

US08344503B2 3-D circuits with integrated passive devices 有权
标题翻译：具有集成无源器件的3-D电路
公开(公告)号：US08344503B2
公开(公告)日：2013-01-01
申请号：US12277519
申请日：2008-11-25
申请人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L23/34
CPC分类号： H01L25/162 , H01L21/6835 , H01L21/76898 , H01L23/3675 , H01L23/481 , H01L23/5384 , H01L23/58 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0296 , H01L27/0629 , H01L28/00 , H01L2221/6835 , H01L2221/68381 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/1147 , H01L2224/13009 , H01L2224/13025 , H01L2224/13147 , H01L2224/16503 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2224/83365 , H01L2224/83385 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2224/81 , H01L2224/13099
摘要： 3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20). The isolator substrate (30) provides superior IPD (38) to AD (26) cross-talk attenuation while permitting each substrate (20, 30, 34) to have small high aspect ratio TSVs (40), facilitating high circuit packing density and efficient manufacturing.
摘要翻译：通过堆叠单独预制的基板（20,30,34），通过穿通基板（20,30,34）耦合而提供具有降低的串扰和高封装密度的集成无源器件（IPD）（38）的3-D IC（18,18'，90） -vias（TSV）（40）。有源器件（AD）衬底（20）在其上部（26）上具有接触。隔离器基板（30）接合到AD基板（20），使得隔离器基板（30）中的TSV（4030）与AD基板（20）上的触点（26）相连，并且希望具有互连区（44）在其上表面。 IPD衬底（34）被结合到隔离器衬底（30），使得其中的TSV（4034）耦合到隔离器衬底（30）上的互连区（44）和/或其中的TSV（4030）。 IPD（38）形成在其上表面上，并由IPD（34）和隔离器（30）衬底中的TSV（4034,4030）与AD衬底（20）中的器件（26）耦合。隔离器基板（30）提供优异的IPD（38）到AD（26）串扰衰减，同时允许每个基板（20,30,34）具有小的高纵横比TSV（40），有利于高电路封装密度和效率制造业。

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