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1. 发明申请

US20110156266A1 METHODS FOR FORMING THROUGH-SUBSTRATE CONDUCTOR FILLED VIAS, AND ELECTRONIC ASSEMBLIES FORMED USING SUCH METHODS 有权
标题翻译：形成通过基底导体填充VIAS的方法和使用这种方法形成的电子组件
公开(公告)号：US20110156266A1
公开(公告)日：2011-06-30
申请号：US13043094
申请日：2011-03-08
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.
摘要翻译：通过用于在非常薄的半导体晶片上进行背面电和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在初始相对较厚的晶片的前表面上形成具有触点的所需器件区域来提供; 在期望的位置部分地通过晶片蚀刻孔; 用连接到一些设备区域接触件的导电材料填充通孔腔; 将晶片的正面安装在支撑结构上; 从背面使晶片变薄以暴露出导电材料填充的通孔的内端; 施加耦合到所述填充通孔的暴露端的任何期望的背面互连区域; 移除支撑结构并分离各个装置或IC组件，以便可用于安装在另外的电路板，带或更大的电路上。

2. 发明申请

US20110272823A1 THROUGH SUBSTRATE VIAS 有权
标题翻译：通过基板VIAS
公开(公告)号：US20110272823A1
公开(公告)日：2011-11-10
申请号：US13188084
申请日：2011-07-21
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/28 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在基本上所有的高温操作之后提供通过衬底通孔（TSV），所述高温操作是通过以下步骤形成靠近衬底晶片的前表面的第一厚度的器件区域：（i）从前表面形成第一方面的较浅的通孔比例包含优选地穿过第一厚度而不是通过初始晶片厚度的第一导体，（ii）从后表面去除材料以形成具有新的后表面的较小最终厚度的改性晶片，以及（iii）从新的后表面，在器件区域下方的第二宽高比的深度更深的通孔，其中其中第二导体接触第一导体，从而在制造和器件区域区域中基本上不影响晶片坚固性而提供前后互连。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

3. 发明申请

US20100264548A1 THROUGH SUBSTRATE VIAS 有权
标题翻译：通过基板VIAS
公开(公告)号：US20100264548A1
公开(公告)日：2010-10-21
申请号：US12425159
申请日：2009-04-16
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30′) of a first aspect ratio containing first conductors (36, 36′) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22″) from the rear surface (22) to form a modified wafer (20′) of smaller final thickness (21′) with a new rear surface (22′), and (iii) forming from the new rear surface (22′), much deeper vias (40, 40′) of second aspect ratios beneath the device region (26) with second conductors (56, 56′) therein contacting the first conductors (36, 36′), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在通过以下方式形成靠近基板晶片（20,20'）的前表面（23）的第一厚度（27）的器件区域（26）所需的基本上所有高温操作之后提供穿过衬底通孔（TSV）：（ i）从前表面（23）形成第一纵横比比较浅的通孔（30,30'），该第一纵横比包含优选地延伸穿过第一厚度（27）但不延伸穿过初始晶片的第一导体（36,36'） 20）厚度（21），（ii）从后表面（22）去除材料（22“）以形成具有新的后表面（22'）的较小最终厚度（21'）的改性晶片（20'），和（iii）从新的后表面（22'）形成在装置区域（26）下面的第二高宽比的更深的通孔（40,40'），其中第二导体（56,56'）在其中接触第一导体 36，36'），从而在制造和器件区域中基本上不影响晶片坚固性，从而提供前后互连区域。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

4. 发明授权

US08329579B2 Through substrate VIAS 有权
标题翻译：通过基底VIAS
公开(公告)号：US08329579B2
公开(公告)日：2012-12-11
申请号：US13188084
申请日：2011-07-21
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/44 , H01L23/04
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在基本上所有的高温操作之后提供通过衬底通孔（TSV），所述高温操作是通过以下步骤形成靠近衬底晶片的前表面的第一厚度的器件区域：（i）从前表面形成第一方面的较浅的通孔比例包含优选地穿过第一厚度而不是通过初始晶片厚度的第一导体，（ii）从后表面去除材料以形成具有新的后表面的较小最终厚度的改性晶片，以及（iii）从新的后表面，在器件区域下方的第二宽高比的深度更深的通孔，其中其中第二导体接触第一导体，从而在制造和器件区域区域中基本上不影响晶片坚固性而提供前后互连。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

5. 发明授权

US08283207B2 Methods for forming through-substrate conductor filled vias, and electronic assemblies formed using such methods 有权
标题翻译：用于形成穿过基底导体的通孔的方法，以及使用这种方法形成的电子组件
公开(公告)号：US08283207B2
公开(公告)日：2012-10-09
申请号：US13043094
申请日：2011-03-08
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L21/44
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.
摘要翻译：通过用于在非常薄的半导体晶片上进行背面电和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在初始相对较厚的晶片的前表面上形成具有触点的所需器件区域来提供; 在期望的位置部分地通过晶片蚀刻孔; 用连接到一些设备区域接触件的导电材料填充通孔腔; 将晶片的正面安装在支撑结构上; 从背面使晶片变薄以暴露出导电材料填充的通孔的内端; 施加耦合到所述填充通孔的暴露端的任何期望的背面互连区域; 移除支撑结构并分离各个装置或IC组件，以便可用于安装在另外的电路板，带或更大的电路上。

6. 发明授权

US07935571B2 Through substrate vias for back-side interconnections on very thin semiconductor wafers 有权
标题翻译：通过用于非常薄的半导体晶片上的背面互连的衬底通孔
公开(公告)号：US07935571B2
公开(公告)日：2011-05-03
申请号：US12277512
申请日：2008-11-25
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L21/44
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18′); etching (104) via cavities (29) partly through the wafer (18′) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18′) with its front side (35) facing a support structure (40); thinning (107) the wafer (18′) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.) of the filled vias; removing (109) the support structure (40) and separating the individual device or IC assemblies (48) so as to be available for mounting (110) on a further circuit board, tape or larger circuit (50).
摘要翻译：通过以下方式提供通过用于在非常薄的半导体晶片上进行背面电气和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在前表面（19）上形成具有触点（22）的期望的器件区域（21）的最初相对较厚的晶片（18'）; 通过腔（29）在期望的位置部分地通过晶片（18'）蚀刻（104）; 通过耦合到一些设备区域触点（22）的导电材料（32）填充（105）所述通孔腔（29）; 安装（106）所述晶片（18'），其前侧（35）面向支撑结构（40）; 从背面（181）将晶片（18'）变薄（107）（107），以暴露导电材料填充的通孔（321,322,323,324等）的内端（3210,3220,3230，3240等））; 施加（108）耦合到所述填充通孔的暴露端（3210,3220,3230,3240等）的任何期望的背面互连区域（44）; 移除（109）支撑结构（40）并分离各个装置或IC组件（48），以便可用于将另一电路板，带或更大的电路（50）安装（110）。

7. 发明申请

US20090243074A1 SEMICONDUCTOR THROUGH SILICON VIAS OF VARIABLE SIZE AND METHOD OF FORMATION 有权
标题翻译：半导体通过可变尺寸的硅VI和形成方法
公开(公告)号：US20090243074A1
公开(公告)日：2009-10-01
申请号：US12059123
申请日：2008-03-31
申请人： Chandrasekaram Ramiah , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Paul W. Sanders
IPC分类号： H01L23/02 , H01L21/02
CPC分类号： H01L21/3065 , H01L21/76816 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.
摘要翻译：通过提供具有形成在其上的第一导电捕获垫和第二导电捕获垫的衬底来形成穿硅通孔结构。衬底被固定到晶片载体上。第一类型的第一蚀刻在第一和第二导电捕捉垫下面的衬底上进行，以形成第一部分通过衬底通孔，第一直径位于第一导电捕获垫下面，第二部分通过衬底通过下面的与第一直径不同的第二直径的第二导电捕获垫。执行与第一类型不同的第二类型的第二蚀刻，以继续蚀刻第一部分通过基板以分别形成相同深度的第一和第二贯穿基板通孔到第一和第二导电捕捉垫。

8. 发明授权

US08344503B2 3-D circuits with integrated passive devices 有权
标题翻译：具有集成无源器件的3-D电路
公开(公告)号：US08344503B2
公开(公告)日：2013-01-01
申请号：US12277519
申请日：2008-11-25
申请人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L23/34
CPC分类号： H01L25/162 , H01L21/6835 , H01L21/76898 , H01L23/3675 , H01L23/481 , H01L23/5384 , H01L23/58 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0296 , H01L27/0629 , H01L28/00 , H01L2221/6835 , H01L2221/68381 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/1147 , H01L2224/13009 , H01L2224/13025 , H01L2224/13147 , H01L2224/16503 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2224/83365 , H01L2224/83385 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2224/81 , H01L2224/13099
摘要： 3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20). The isolator substrate (30) provides superior IPD (38) to AD (26) cross-talk attenuation while permitting each substrate (20, 30, 34) to have small high aspect ratio TSVs (40), facilitating high circuit packing density and efficient manufacturing.
摘要翻译：通过堆叠单独预制的基板（20,30,34），通过穿通基板（20,30,34）耦合而提供具有降低的串扰和高封装密度的集成无源器件（IPD）（38）的3-D IC（18,18'，90） -vias（TSV）（40）。有源器件（AD）衬底（20）在其上部（26）上具有接触。隔离器基板（30）接合到AD基板（20），使得隔离器基板（30）中的TSV（4030）与AD基板（20）上的触点（26）相连，并且希望具有互连区（44）在其上表面。 IPD衬底（34）被结合到隔离器衬底（30），使得其中的TSV（4034）耦合到隔离器衬底（30）上的互连区（44）和/或其中的TSV（4030）。 IPD（38）形成在其上表面上，并由IPD（34）和隔离器（30）衬底中的TSV（4034,4030）与AD衬底（20）中的器件（26）耦合。隔离器基板（30）提供优异的IPD（38）到AD（26）串扰衰减，同时允许每个基板（20,30,34）具有小的高纵横比TSV（40），有利于高电路封装密度和效率制造业。

9. 发明授权

US08062975B2 Through substrate vias 有权
标题翻译：通过衬底通孔
公开(公告)号：US08062975B2
公开(公告)日：2011-11-22
申请号：US12425159
申请日：2009-04-16
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30′) of a first aspect ratio containing first conductors (36, 36′) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22″) from the rear surface (22) to form a modified wafer (20′) of smaller final thickness (21′) with a new rear surface (22′), and (iii) forming from the new rear surface (22′), much deeper vias (40, 40′) of second aspect ratios beneath the device region (26) with second conductors (56, 56′) therein contacting the first conductors (36, 36′), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在通过以下方式形成靠近基板晶片（20,20'）的前表面（23）的第一厚度（27）的器件区域（26）所需的基本上所有高温操作之后提供穿过衬底通孔（TSV）：（ i）从前表面（23）形成第一纵横比比较浅的通孔（30,30'），该第一纵横比包含优选地延伸穿过第一厚度（27）但不延伸穿过初始晶片的第一导体（36,36'） 20）厚度（21），（ii）从后表面（22）去除材料（22“）以形成具有新的后表面（22'）的较小最终厚度（21'）的改性晶片（20'），和（iii）从新的后表面（22'）形成在装置区域（26）下面的第二高宽比的更深的通孔（40,40'），其中第二导体（56,56'）在其中接触第一导体 36，36'），从而在制造和器件区域中基本上不影响晶片坚固性，从而提供前后互连区域。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

10. 发明申请

US20100127345A1 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES 有权
标题翻译：具有集成无源器件的3-D电路
公开(公告)号：US20100127345A1
公开(公告)日：2010-05-27
申请号：US12277519
申请日：2008-11-25
申请人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L29/00 , H01L21/60
CPC分类号： H01L25/162 , H01L21/6835 , H01L21/76898 , H01L23/3675 , H01L23/481 , H01L23/5384 , H01L23/58 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0296 , H01L27/0629 , H01L28/00 , H01L2221/6835 , H01L2221/68381 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/1147 , H01L2224/13009 , H01L2224/13025 , H01L2224/13147 , H01L2224/16503 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2224/83365 , H01L2224/83385 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2224/81 , H01L2224/13099
摘要： 3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20). The isolator substrate (30) provides superior IPD (38) to AD (26) cross-talk attenuation while permitting each substrate (20, 30, 34) to have small high aspect ratio TSVs (40), facilitating high circuit packing density and efficient manufacturing.
摘要翻译：通过堆叠单独预制的基板（20,30,34），通过穿通基板（20,30,34）耦合而提供具有降低的串扰和高封装密度的集成无源器件（IPD）（38）的3-D IC（18,18'，90） -vias（TSV）（40）。有源器件（AD）衬底（20）在其上部（26）上具有接触。隔离器基板（30）接合到AD基板（20），使得隔离器基板（30）中的TSV（4030）与AD基板（20）上的触点（26）相连，并且希望具有互连区（44）在其上表面。 IPD衬底（34）被结合到隔离器衬底（30），使得其中的TSV（4034）耦合到隔离器衬底（30）上的互连区（44）和/或其中的TSV（4030）。 IPD（38）形成在其上表面上，并且在IPD（34）和隔离器（30）衬底中的TSV（4034,4030）与AD衬底（20）中的器件（26）耦合。隔离器基板（30）提供优异的IPD（38）到AD（26）串扰衰减，同时允许每个基板（20,30,34）具有小的高纵横比TSV（40），有利于高电路封装密度和效率制造业。

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