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1. 发明授权

US09064712B2 Monolithic microwave integrated circuit 有权
标题翻译：单片微波集成电路
公开(公告)号：US09064712B2
公开(公告)日：2015-06-23
申请号：US12855479
申请日：2010-08-12
申请人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
发明人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
IPC分类号： H01L23/522 , H01L27/06 , H01L23/48 , H01L23/66 , H03F3/195 , H01L23/00
CPC分类号： H01L23/66 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L27/0617 , H01L27/0629 , H01L27/0727 , H01L28/10 , H01L28/40 , H01L29/7816 , H01L2223/6616 , H01L2223/6655 , H01L2223/6683 , H01L2224/48091 , H01L2224/49175 , H01L2225/06541 , H01L2924/00014 , H01L2924/12044 , H01L2924/13062 , H01L2924/14 , H01L2924/1423 , H01L2924/30107 , H03F3/195 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.
摘要翻译：使用高电阻率（例如≥100欧姆 - 厘米）的半导体衬底（60）和较低电阻电感（44'，45'）可以避免或减轻以微波频率操作时与单片集成电路（IC）的无源部件相关的低Q，）用于IC（46）。这消除了覆盖衬底（60）的平面电感器（44,45）和互连（50-1'，52-1'，94,94'，94“）的显着的衬底内电磁耦合损耗。有源晶体管（41'）在靠近前表面（63）的基底（60）中形成。平面电容器（42'，43'）也形成在衬底（60）的前表面（63）上方。晶体管的各个端子（42-1'，42-2'，43-1,43-2'，50'，51'，52'，42-1'，42-2'等）（41'），电容器（42'，43'）和电感器（44'，45'）耦合到衬底（60）的背面（62）上的接地平面（69）使用贯通衬底通孔（98,98'）来最小化寄生电阻。通过将平面电感器（44'，45'）和大电流承载导体（52-1'）相关联的寄生电阻放置在IC的外表面上，使其可以被制成基本上更厚且电阻更低。其结果是先前无法获得的单片微波IC（46,58）。

2. 发明申请

US20120037969A1 MONOLITHIC MICROWAVE INTEGRATED CIRCUIT 有权
标题翻译：单片微波集成电路
公开(公告)号：US20120037969A1
公开(公告)日：2012-02-16
申请号：US12855479
申请日：2010-08-12
申请人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
发明人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L23/66 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L27/0617 , H01L27/0629 , H01L27/0727 , H01L28/10 , H01L28/40 , H01L29/7816 , H01L2223/6616 , H01L2223/6655 , H01L2223/6683 , H01L2224/48091 , H01L2224/49175 , H01L2225/06541 , H01L2924/00014 , H01L2924/12044 , H01L2924/13062 , H01L2924/14 , H01L2924/1423 , H01L2924/30107 , H03F3/195 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.
摘要翻译：使用高电阻率（例如≥100欧姆 - 厘米）的半导体衬底（60）和较低电阻电感（44'，45'）可以避免或减轻以微波频率操作时与单片集成电路（IC）的无源部件相关的低Q，）用于IC（46）。这消除了覆盖衬底（60）的平面电感器（44,45）和互连（50-1'，52-1'，94,94'，94“）的显着的衬底内电磁耦合损耗。有源晶体管（41'）在靠近前表面（63）的基底（60）中形成。平面电容器（42'，43'）也形成在衬底（60）的前表面（63）上方。晶体管的各个端子（42-1'，42-2'，43-1,43-2'，50'，51'，52'，42-1'，42-2'等）（41'），电容器（42'，43'）和电感器（44'，45'）耦合到衬底（60）的背面（62）上的接地平面（69）使用贯通衬底通孔（98,98'）来最小化寄生电阻。通过将平面电感器（44'，45'）和大电流承载导体（52-1'）相关联的寄生电阻放置在IC的外表面上，使其可以被制成基本上更厚且电阻更低。其结果是先前无法获得的单片微波IC（46,58）。

3. 发明授权

US08518764B2 Semiconductor structure having a through substrate via (TSV) and method for forming 有权
标题翻译：具有贯通基板通孔（TSV）的半导体结构及其形成方法
公开(公告)号：US08518764B2
公开(公告)日：2013-08-27
申请号：US13279776
申请日：2011-10-24
申请人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
发明人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L21/76898 , H01L21/26586 , H01L23/5227 , H01L23/66 , H01L28/10 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/7835 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.
摘要翻译：半导体器件结构包括具有第一浓度和第一导电类型的背景掺杂的衬底。贯穿基板通孔（TSV）通过基板。器件在衬底的第一侧上具有第二导电性的第一掺杂区域。第二掺杂区域在TSV周围。第二掺杂区具有大于第一浓度的第二浓度的掺杂并且是第一导电类型。

4. 发明申请

US20130099312A1 SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING 有权
标题翻译：具有通过（TSV）的基底的半导体结构和形成方法
公开(公告)号：US20130099312A1
公开(公告)日：2013-04-25
申请号：US13279776
申请日：2011-10-24
申请人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
发明人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
IPC分类号： H01L29/78 , H01L21/225
CPC分类号： H01L21/76898 , H01L21/26586 , H01L23/5227 , H01L23/66 , H01L28/10 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/7835 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.
摘要翻译：半导体器件结构包括具有第一浓度和第一导电类型的背景掺杂的衬底。贯穿基板通孔（TSV）通过基板。器件在衬底的第一侧上具有第二导电性的第一掺杂区域。第二掺杂区域在TSV周围。第二掺杂区具有大于第一浓度的第二浓度的掺杂并且是第一导电类型。

5. 发明申请

US20110272823A1 THROUGH SUBSTRATE VIAS 有权
标题翻译：通过基板VIAS
公开(公告)号：US20110272823A1
公开(公告)日：2011-11-10
申请号：US13188084
申请日：2011-07-21
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/28 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在基本上所有的高温操作之后提供通过衬底通孔（TSV），所述高温操作是通过以下步骤形成靠近衬底晶片的前表面的第一厚度的器件区域：（i）从前表面形成第一方面的较浅的通孔比例包含优选地穿过第一厚度而不是通过初始晶片厚度的第一导体，（ii）从后表面去除材料以形成具有新的后表面的较小最终厚度的改性晶片，以及（iii）从新的后表面，在器件区域下方的第二宽高比的深度更深的通孔，其中其中第二导体接触第一导体，从而在制造和器件区域区域中基本上不影响晶片坚固性而提供前后互连。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

6. 发明申请

US20100264548A1 THROUGH SUBSTRATE VIAS 有权
标题翻译：通过基板VIAS
公开(公告)号：US20100264548A1
公开(公告)日：2010-10-21
申请号：US12425159
申请日：2009-04-16
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30′) of a first aspect ratio containing first conductors (36, 36′) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22″) from the rear surface (22) to form a modified wafer (20′) of smaller final thickness (21′) with a new rear surface (22′), and (iii) forming from the new rear surface (22′), much deeper vias (40, 40′) of second aspect ratios beneath the device region (26) with second conductors (56, 56′) therein contacting the first conductors (36, 36′), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在通过以下方式形成靠近基板晶片（20,20'）的前表面（23）的第一厚度（27）的器件区域（26）所需的基本上所有高温操作之后提供穿过衬底通孔（TSV）：（ i）从前表面（23）形成第一纵横比比较浅的通孔（30,30'），该第一纵横比包含优选地延伸穿过第一厚度（27）但不延伸穿过初始晶片的第一导体（36,36'） 20）厚度（21），（ii）从后表面（22）去除材料（22“）以形成具有新的后表面（22'）的较小最终厚度（21'）的改性晶片（20'），和（iii）从新的后表面（22'）形成在装置区域（26）下面的第二高宽比的更深的通孔（40,40'），其中第二导体（56,56'）在其中接触第一导体 36，36'），从而在制造和器件区域中基本上不影响晶片坚固性，从而提供前后互连区域。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

7. 发明授权

US08329579B2 Through substrate VIAS 有权
标题翻译：通过基底VIAS
公开(公告)号：US08329579B2
公开(公告)日：2012-12-11
申请号：US13188084
申请日：2011-07-21
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/44 , H01L23/04
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在基本上所有的高温操作之后提供通过衬底通孔（TSV），所述高温操作是通过以下步骤形成靠近衬底晶片的前表面的第一厚度的器件区域：（i）从前表面形成第一方面的较浅的通孔比例包含优选地穿过第一厚度而不是通过初始晶片厚度的第一导体，（ii）从后表面去除材料以形成具有新的后表面的较小最终厚度的改性晶片，以及（iii）从新的后表面，在器件区域下方的第二宽高比的深度更深的通孔，其中其中第二导体接触第一导体，从而在制造和器件区域区域中基本上不影响晶片坚固性而提供前后互连。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

8. 发明授权

US08283207B2 Methods for forming through-substrate conductor filled vias, and electronic assemblies formed using such methods 有权
标题翻译：用于形成穿过基底导体的通孔的方法，以及使用这种方法形成的电子组件
公开(公告)号：US08283207B2
公开(公告)日：2012-10-09
申请号：US13043094
申请日：2011-03-08
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L21/44
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.
摘要翻译：通过用于在非常薄的半导体晶片上进行背面电和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在初始相对较厚的晶片的前表面上形成具有触点的所需器件区域来提供; 在期望的位置部分地通过晶片蚀刻孔; 用连接到一些设备区域接触件的导电材料填充通孔腔; 将晶片的正面安装在支撑结构上; 从背面使晶片变薄以暴露出导电材料填充的通孔的内端; 施加耦合到所述填充通孔的暴露端的任何期望的背面互连区域; 移除支撑结构并分离各个装置或IC组件，以便可用于安装在另外的电路板，带或更大的电路上。

9. 发明授权

US07935571B2 Through substrate vias for back-side interconnections on very thin semiconductor wafers 有权
标题翻译：通过用于非常薄的半导体晶片上的背面互连的衬底通孔
公开(公告)号：US07935571B2
公开(公告)日：2011-05-03
申请号：US12277512
申请日：2008-11-25
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L21/44
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18′); etching (104) via cavities (29) partly through the wafer (18′) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18′) with its front side (35) facing a support structure (40); thinning (107) the wafer (18′) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.) of the filled vias; removing (109) the support structure (40) and separating the individual device or IC assemblies (48) so as to be available for mounting (110) on a further circuit board, tape or larger circuit (50).
摘要翻译：通过以下方式提供通过用于在非常薄的半导体晶片上进行背面电气和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在前表面（19）上形成具有触点（22）的期望的器件区域（21）的最初相对较厚的晶片（18'）; 通过腔（29）在期望的位置部分地通过晶片（18'）蚀刻（104）; 通过耦合到一些设备区域触点（22）的导电材料（32）填充（105）所述通孔腔（29）; 安装（106）所述晶片（18'），其前侧（35）面向支撑结构（40）; 从背面（181）将晶片（18'）变薄（107）（107），以暴露导电材料填充的通孔（321,322,323,324等）的内端（3210,3220,3230，3240等））; 施加（108）耦合到所述填充通孔的暴露端（3210,3220,3230,3240等）的任何期望的背面互连区域（44）; 移除（109）支撑结构（40）并分离各个装置或IC组件（48），以便可用于将另一电路板，带或更大的电路（50）安装（110）。

10. 发明申请

US20100127394A1 THROUGH SUBSTRATE VIAS FOR BACK-SIDE INTERCONNECTIONS ON VERY THIN SEMICONDUCTOR WAFERS 有权
标题翻译：通过基板VIAS在非常薄的半导体波形上进行背面互连
公开(公告)号：US20100127394A1
公开(公告)日：2010-05-27
申请号：US12277512
申请日：2008-11-25
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L23/528 , H01L21/768 , H01L23/532
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18′); etching (104) via cavities (29) partly through the wafer (18′) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18′) with its front side (35) facing a support structure (40); thinning (107) the wafer (18′) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.) of the filled vias; removing (109) the support structure (40) and separating the individual device or IC assemblies (48) so as to be available for mounting (110) on a further circuit board, tape or larger circuit (50).
摘要翻译：通过以下方式提供通过用于在非常薄的半导体晶片上进行背面电气和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在前表面（19）上形成具有触点（22）的期望的器件区域（21）的最初相对较厚的晶片（18'）; 通过腔（29）在期望的位置部分地通过晶片（18'）蚀刻（104）; 通过耦合到一些设备区域触点（22）的导电材料（32）填充（105）所述通孔腔（29）; 安装（106）所述晶片（18'），其前侧（35）面向支撑结构（40）; 从背面（181）将晶片（18'）变薄（107）（107），以暴露导电材料填充的通孔（321,322,323,324等）的内端（3210,3220,3230，3240等））; 施加（108）耦合到所述填充通孔的暴露端（3210,3220,3230,3240等）的任何期望的背面互连区域（44）; 移除（109）支撑结构（40）并分离各个装置或IC组件（48），以便可用于将另一电路板，带或更大的电路（50）安装（110）。

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