专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4649630A Process for dielectrically isolated semiconductor structure 失效
标题翻译：介电隔离半导体结构的工艺
公开(公告)号：US4649630A
公开(公告)日：1987-03-17
申请号：US718255
申请日：1985-04-01
申请人： Bernard W. Boland , Paul W. Sanders
发明人： Bernard W. Boland , Paul W. Sanders
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76297 , Y10S148/043 , Y10S148/085 , Y10S148/122 , Y10S438/928 , Y10S438/969 , Y10S438/977
摘要： A process is disclosed for controllably providing dielectrically isolated semiconductor regions having a uniform and well defined thickness. Grooves are formed in a first surface of a semiconductor substrate and then a dielectric layer is formed covering that surface and the grooves extending into the surface. A layer of backing material such as polycrystalline silicon is formed overlying the dielectric layer. A semiconductor substrate is then thinned to form a new surface with portions of the dielectric layer and backing material exposed at that surface. A semiconductor layer is epitaxially grown overlying the new surface with the semiconductor layer having a monocrystalline structure where it is grown on exposed regions of the original substrate and having a polycrystalline structure otherwise. An oxidation masking layer is formed overlying those portions of the semiconductor layer which have a monocrystalline structure. Those portions of the semiconductor layer which are not covered by the oxidation masking layer are then oxidized to form an oxide extending through the semiconductor layer to the underlying dielectric layer. This oxide plus the original dielectric layer thus surround and isolate individual regions in which a portion of the original substrate has an epitaxial layer of semiconductor material grown thereon.
摘要翻译：公开了一种用于可控地提供具有均匀且良好限定厚度的介电隔离的半导体区域的方法。在半导体衬底的第一表面中形成沟槽，然后形成覆盖该表面的电介质层和延伸到表面中的沟槽。形成覆盖在电介质层上的诸如多晶硅的背衬材料层。然后将半导体衬底变薄以形成新的表面，其中介电层和背衬材料的部分暴露在该表面。外延生长半导体层，其中半导体层具有单晶结构，其中它生长在原始衬底的暴露区域上，否则具有多晶结构。在半导体层的具有单晶结构的那些部分上形成氧化掩模层。未被氧化掩模层覆盖的半导体层的那些部分然后被氧化，以形成延伸穿过半导体层的氧化物到下面的介电层。因此，该氧化物加上原始电介质层围绕并隔离其中原始衬底的一部分具有在其上生长的半导体材料的外延层的各个区域。

2. 发明授权

US5145795A Semiconductor device and method therefore 失效
标题翻译：半导体器件及其方法
公开(公告)号：US5145795A
公开(公告)日：1992-09-08
申请号：US543233
申请日：1990-06-25
申请人： Paul W. Sanders , Bernard W. Boland
发明人： Paul W. Sanders , Bernard W. Boland
IPC分类号： H01L21/762
CPC分类号： H01L21/76297 , H01L2224/48091 , H01L2224/73265 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , Y10S148/168 , Y10S438/977
摘要： An improved high frequency dielectrically isolated (DIC) transistor (100) or integrated circuit is obtained by providing a highly doped single crystal semiconductor region (112) coupled to the device reference terminal (16') and extending between front (98) and rear (61) faces of the semiconductor die. This allows the reference terminal (16', 116) to be coupled to the package ground plane without use of wire bonds, thereby lowering the common mode impedance. The desired structure is formed in connection with DIC devices (100) by etching first (66) and second (77) nested cavities into a single crystal substrate (60). The cavities (66) form protruding islands (821, 822) of single crystal semiconductor having a height (80+68) about equal the final die thickness (110) and which, after conventional DIC processing using an oxide isolation layer (86) and a poly handle (88), are exposed by grinding away the poly handle (88) to expose the highly doped, single crystal reference terminal feed-through (112).
摘要翻译：通过提供耦合到器件参考端子（16'）并在前面（98）和后面（98）之间延伸的高掺杂单晶半导体区域（112），获得改进的高频介电隔离（DIC）晶体管（100）或集成电路 61）面。这允许参考端子（16'，116）在不使用引线接合的情况下耦合到封装接地层，从而降低共模阻抗。通过将第一（66）和第二（77）嵌套空穴蚀刻到单晶衬底（60）中，与DIC器件（100）相关地形成期望的结构。空腔（66）形成高度（80 + 68）的大约等于最终管芯厚度（110）的单晶半导体的突出岛（821,822），并且在使用氧化物隔离层（86）的常规DIC处理和通过研磨多晶硅手柄（88）以暴露高度掺杂的单晶参考端子馈通（112）来暴露多晶硅手柄（88）。

3. 发明授权

US5254491A Method of making a semiconductor device having improved frequency response 失效
标题翻译：制造具有改善的频率响应的半导体器件的方法
公开(公告)号：US5254491A
公开(公告)日：1993-10-19
申请号：US763773
申请日：1991-09-23
申请人： Bernard W. Boland , Robert B. Davies , Paul W. Sanders
发明人： Bernard W. Boland , Robert B. Davies , Paul W. Sanders
IPC分类号： H01L21/762 , H01L21/763 , H01L29/78 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/763
摘要： A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

4. 发明授权

US5001075A Fabrication of dielectrically isolated semiconductor device 失效
标题翻译：介电绝缘半导体器件的制造
公开(公告)号：US5001075A
公开(公告)日：1991-03-19
申请号：US333065
申请日：1989-04-03
申请人： Bernard W. Boland , Paul W. Sanders
发明人： Bernard W. Boland , Paul W. Sanders
IPC分类号： H01L29/73 , H01L21/331 , H01L21/762 , H01L21/8222 , H01L27/06 , H01L29/732
CPC分类号： H01L21/76297
摘要： Improved dielectrically isolated semiconductor structures especially suited for very high frequency bipolar transistors are produced. Recesses are formed in a (e.g., N.sup.+) single crystal semiconductor wafer, the wafer surface is coated with a dielectric, and a thick polycrystalline semiconductor layer is deposited thereon to provide a support. The single crystal wafer is back-lapped to expose dielectrically isolated N.sup.+ islands located between the original recesses. Depressions are etched in the N.sup.+ islands and the exposed surface is covered by a more lightly doped (e.g., N.sup.-) semiconductor layer which is, generally, single crystal above the N.sup.+ islands and non-single crystal therebetween, and which at least fills the depressions. The structure is then planarized (e.g., by lapping and etching) to remove this non-single crystal material and give isolated single crystal islands having a surrounding N.sup.+ periphery and an N.sup.- central epi region of well controlled thickness and a smooth outer surface suitable for device formation. Bipolar transistors of excellent properties are formed by providing a nested base and emitter within the central region. Other types of devices may also be formed. The surrounding N.sup.+ periphery automatically provides a buried layer and buried layer contact.

5. 发明申请

US20130129714A1 PREVENTION AND TREATMENT OF CAST NEPHROPATHY 有权
标题翻译：预防和治疗慢性阻塞性肺疾病
公开(公告)号：US20130129714A1
公开(公告)日：2013-05-23
申请号：US13639002
申请日：2011-04-01
申请人： Paul W. Sanders
发明人： Paul W. Sanders
IPC分类号： C07K7/08 , C12N15/113 , C07K16/42
CPC分类号： C07K7/08 , A61K38/00 , C07K14/47 , C07K16/4241 , C07K2317/515 , C07K2317/565 , C12N15/113 , C12N2310/11 , C12N2310/14
摘要： Provided herein are polypeptides comprising or consisting essentially of a QSYDNTLSGSYVF (SEQ ID NO:1) or LSADSSGSYLYVF (SEQ ID NO:2) amino acid sequence. Also provided herein are methods of treating or preventing cast nephropathy in a subject. The methods comprise identifying a subject with or at risk of developing cast nephropathy and administering to the subject any of the polypeptides disclosed herein.
摘要翻译：本文提供的是包含或基本上由QSYDNTLSGSYVF（SEQ ID NO：1）或LSADSSGSYLYVF（SEQ ID NO：2）氨基酸序列组成的多肽。本文还提供了治疗或预防受试者中的肾性肾病的方法。所述方法包括鉴定患有或具有发展为流产性肾病的风险的受试者，并向受试者施用本文公开的任何多肽。

6. 发明申请

US20110272823A1 THROUGH SUBSTRATE VIAS 有权
标题翻译：通过基板VIAS
公开(公告)号：US20110272823A1
公开(公告)日：2011-11-10
申请号：US13188084
申请日：2011-07-21
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/28 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在基本上所有的高温操作之后提供通过衬底通孔（TSV），所述高温操作是通过以下步骤形成靠近衬底晶片的前表面的第一厚度的器件区域：（i）从前表面形成第一方面的较浅的通孔比例包含优选地穿过第一厚度而不是通过初始晶片厚度的第一导体，（ii）从后表面去除材料以形成具有新的后表面的较小最终厚度的改性晶片，以及（iii）从新的后表面，在器件区域下方的第二宽高比的深度更深的通孔，其中其中第二导体接触第一导体，从而在制造和器件区域区域中基本上不影响晶片坚固性而提供前后互连。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

7. 发明申请

US20100264548A1 THROUGH SUBSTRATE VIAS 有权
标题翻译：通过基板VIAS
公开(公告)号：US20100264548A1
公开(公告)日：2010-10-21
申请号：US12425159
申请日：2009-04-16
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30′) of a first aspect ratio containing first conductors (36, 36′) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22″) from the rear surface (22) to form a modified wafer (20′) of smaller final thickness (21′) with a new rear surface (22′), and (iii) forming from the new rear surface (22′), much deeper vias (40, 40′) of second aspect ratios beneath the device region (26) with second conductors (56, 56′) therein contacting the first conductors (36, 36′), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在通过以下方式形成靠近基板晶片（20,20'）的前表面（23）的第一厚度（27）的器件区域（26）所需的基本上所有高温操作之后提供穿过衬底通孔（TSV）：（ i）从前表面（23）形成第一纵横比比较浅的通孔（30,30'），该第一纵横比包含优选地延伸穿过第一厚度（27）但不延伸穿过初始晶片的第一导体（36,36'） 20）厚度（21），（ii）从后表面（22）去除材料（22“）以形成具有新的后表面（22'）的较小最终厚度（21'）的改性晶片（20'），和（iii）从新的后表面（22'）形成在装置区域（26）下面的第二高宽比的更深的通孔（40,40'），其中第二导体（56,56'）在其中接触第一导体 36，36'），从而在制造和器件区域中基本上不影响晶片坚固性，从而提供前后互连区域。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

8. 发明授权

US5734194A Semiconductor device and method of making 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5734194A
公开(公告)日：1998-03-31
申请号：US792602
申请日：1997-01-31
申请人： Paul W. Sanders , Troy E. Mackie , Julio C. Costa , John L. Freeman, Jr. , Alan D. Wood
发明人： Paul W. Sanders , Troy E. Mackie , Julio C. Costa , John L. Freeman, Jr. , Alan D. Wood
IPC分类号： H01L29/73 , H01L21/265 , H01L21/331 , H01L29/08 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/0821 , H01L29/7322
摘要： A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).
摘要翻译：半导体器件（10）形成在用作集电极区域的半导体衬底（11）中。在半导体衬底（11）中形成基极区（12），并且形成发射极区（52），使其与基极区（12）的至少一部分相接触。导电层（28）用于提供与发射极区域（52）的电连接。在发射极区域（52）上方的导电层（28）的部分被反掺杂以解决存在于发射极区域（52）和导电层（28）之间的界面氧化物层（27）的问题。

9. 发明申请

US20120037969A1 MONOLITHIC MICROWAVE INTEGRATED CIRCUIT 有权
标题翻译：单片微波集成电路
公开(公告)号：US20120037969A1
公开(公告)日：2012-02-16
申请号：US12855479
申请日：2010-08-12
申请人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
发明人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L23/66 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L27/0617 , H01L27/0629 , H01L27/0727 , H01L28/10 , H01L28/40 , H01L29/7816 , H01L2223/6616 , H01L2223/6655 , H01L2223/6683 , H01L2224/48091 , H01L2224/49175 , H01L2225/06541 , H01L2924/00014 , H01L2924/12044 , H01L2924/13062 , H01L2924/14 , H01L2924/1423 , H01L2924/30107 , H03F3/195 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.
摘要翻译：使用高电阻率（例如≥100欧姆 - 厘米）的半导体衬底（60）和较低电阻电感（44'，45'）可以避免或减轻以微波频率操作时与单片集成电路（IC）的无源部件相关的低Q，）用于IC（46）。这消除了覆盖衬底（60）的平面电感器（44,45）和互连（50-1'，52-1'，94,94'，94“）的显着的衬底内电磁耦合损耗。有源晶体管（41'）在靠近前表面（63）的基底（60）中形成。平面电容器（42'，43'）也形成在衬底（60）的前表面（63）上方。晶体管的各个端子（42-1'，42-2'，43-1,43-2'，50'，51'，52'，42-1'，42-2'等）（41'），电容器（42'，43'）和电感器（44'，45'）耦合到衬底（60）的背面（62）上的接地平面（69）使用贯通衬底通孔（98,98'）来最小化寄生电阻。通过将平面电感器（44'，45'）和大电流承载导体（52-1'）相关联的寄生电阻放置在IC的外表面上，使其可以被制成基本上更厚且电阻更低。其结果是先前无法获得的单片微波IC（46,58）。

10. 发明申请

US20110156266A1 METHODS FOR FORMING THROUGH-SUBSTRATE CONDUCTOR FILLED VIAS, AND ELECTRONIC ASSEMBLIES FORMED USING SUCH METHODS 有权
标题翻译：形成通过基底导体填充VIAS的方法和使用这种方法形成的电子组件
公开(公告)号：US20110156266A1
公开(公告)日：2011-06-30
申请号：US13043094
申请日：2011-03-08
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.
摘要翻译：通过用于在非常薄的半导体晶片上进行背面电和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在初始相对较厚的晶片的前表面上形成具有触点的所需器件区域来提供; 在期望的位置部分地通过晶片蚀刻孔; 用连接到一些设备区域接触件的导电材料填充通孔腔; 将晶片的正面安装在支撑结构上; 从背面使晶片变薄以暴露出导电材料填充的通孔的内端; 施加耦合到所述填充通孔的暴露端的任何期望的背面互连区域; 移除支撑结构并分离各个装置或IC组件，以便可用于安装在另外的电路板，带或更大的电路上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式