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1. 发明授权

US4695950A Fast two-level dynamic address translation method and means 失效
标题翻译：快速二级动态地址转换方法和手段
公开(公告)号：US4695950A
公开(公告)日：1987-09-22
申请号：US651491
申请日：1984-09-17
申请人： Henry R. Brandt , Patrick M. Gannon , Wan L. Leung , Timothy R. Marchini
发明人： Henry R. Brandt , Patrick M. Gannon , Wan L. Leung , Timothy R. Marchini
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1036 , G06F12/145
摘要： A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.
摘要翻译：一种独特的高速硬件安排，用于生成双层地址转换，并结合翻译后备缓冲区（TLB）结构，可在双级转换期间存储和查找中间翻译。虽然遇到中间TLB未命中，但不会发生CPU死锁的危险，硬件继续完成双级转换，而不必备份其操作。硬件安排还执行系统所需的所有单级地址转换。

2. 发明授权

US4157586A Technique for performing partial stores in store-thru memory configuration 失效
标题翻译：在存储器存储器配置中执行部分存储的技术
公开(公告)号：US4157586A
公开(公告)日：1979-06-05
申请号：US794323
申请日：1977-05-05
申请人： Patrick M. Gannon , Julius D. Jones , Dale M. Junod , Richard L. Partridge , Thomas R. Wright
发明人： Patrick M. Gannon , Julius D. Jones , Dale M. Junod , Richard L. Partridge , Thomas R. Wright
IPC分类号： G06F12/04 , G06F12/08 , G06F7/02
CPC分类号： G06F12/0804
摘要： This specification relates to performance of partial store operation in a hierarchical memory system which has a buffer store interposed between a processor interrogating the memory system and the main memory of the memory system. Such a partial store operation can be performed on a word of data in the main memory using the buffer store copy of that word of data. The copy of the word of data is read out of the buffer store into a register where it is modified to form a new word by replacing one or more but not all of the bytes in the word of data with bytes supplied by the processor. The new word is then placed in the main memory by performing a full store operation. The problem with performing a partial store operation in this manner is that the copy of the word of data in the buffer store may not be up-to-date. A technique is provided to eliminate the possibility of this old data being rewritten back into the main memory.
摘要翻译：本说明书涉及在分层存储器系统中的部分存储操作的性能，其具有插入在询问存储器系统的处理器和存储器系统的主存储器之间的缓冲存储器。可以使用该数据字的缓冲存储副本对主存储器中的数据字执行这种部分存储操作。将数据字的副本从缓冲存储器中读出到寄存器中，在该寄存器中，通过用处理器提供的字节替换数据字中的一个或多个但不是全部的字节来修改它来形成新的字。然后通过执行完整的存储操作将新的字放置在主存储器中。以这种方式执行部分存储操作的问题是缓冲存储器中的数据字的副本可能不是最新的。提供了一种技术来消除将旧数据重写回主存储器的可能性。

3. 发明授权

US4149245A High speed store request processing control 失效
标题翻译：高速存储请求处理控制
公开(公告)号：US4149245A
公开(公告)日：1979-04-10
申请号：US805065
申请日：1977-06-09
申请人： Patrick M. Gannon , Kian-Bon K. Sy
发明人： Patrick M. Gannon , Kian-Bon K. Sy
IPC分类号： G06F12/08 , G06F9/34 , G06F12/00 , G06F12/06 , G06F13/16 , G06F13/06 , G06F9/18
CPC分类号： G06F13/161
摘要： The described embodiment provides storage control (PSCF) for overlapping the handling of processor store requests between their generation by an instruction execution means (IPPF) and their presentation to system main storage (MS).The embodiment uses a store counter, an inpointer counter, an outpointer counter, a translator pointer register, an output counter and a plurality of registers sets to process and control the sequencing of all store requests so that the PSCF can output them to MS in the order received from the IPPF. The embodiment uses the counters to coordinate the varying delays in PSCF processing of plural store request contained in different register sets and the translator.The store counter obtains independence between plural IPPF operand address (OA) registers which send the store requests and plural PSCF register sets which handle the store request. The number of OA registers is made independent of the number of register sets. The store counter is also used for serializing instruction control.
摘要翻译：所描述的实施例提供了存储控制（PSCF），用于通过指令执行装置（IPPF）及其对系统主存储（MS）的呈现之间的处理来重叠处理器存储请求的处理。

4. 发明授权

US5317705A Apparatus and method for TLB purge reduction in a multi-level machine system 失效
标题翻译：用于多级机器系统中TLB吹扫减少的装置和方法
公开(公告)号：US5317705A
公开(公告)日：1994-05-31
申请号：US112174
申请日：1993-08-26
申请人： Patrick M. Gannon , Peter H. Gum , Roger E. Hough , Robert E. Murray
发明人： Patrick M. Gannon , Peter H. Gum , Roger E. Hough , Robert E. Murray
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/1036
摘要： A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB. This time saving results in increased performance in systems with multi-level guests.
摘要翻译：用于减少翻译后备缓冲器（TLB）的清除以减少运行多级虚拟机的系统中的操作系统开销的系统。由于主机或基础客机上的分页活动，每当基础页表项无效时，系统通常必须清除TLB条目。提供了一种用于减少客户转换基于主机页表项的情况的系统。提供附加逻辑来分析每个无效页表项（IPTE）指令，以最小化该指令所需的清除范围。当区域重新定位设施正在运行时，或者当没有构建可页面的TLB时，只需要清除与该页表项对应的条目即可。这种有限的清除通过减少清除时间和地址转换所需的时间来重建TLB来减少开销。节省时间可以提高具有多级客人的系统的性能。

5. 发明授权

US5265232A Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data 失效
标题翻译：在所选处理器高速缓存中通过数据无效的一致性控制，而无需广播到不具有数据的处理器缓存
公开(公告)号：US5265232A
公开(公告)日：1993-11-23
申请号：US679900
申请日：1991-04-03
申请人： Patrick M. Gannon , Michael Ignatowski , Matthew A. Krygowski , Lishing Liu , Donald W. Price , William K. Rodiger , Gregory Salyer , Yee-Ming Ting , Michael P. Witt
发明人： Patrick M. Gannon , Michael Ignatowski , Matthew A. Krygowski , Lishing Liu , Donald W. Price , William K. Rodiger , Gregory Salyer , Yee-Ming Ting , Michael P. Witt
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/082 , G06F12/0811
摘要： A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).

6. 发明授权

US4189770A Cache bypass control for operand fetches 失效
标题翻译：缓存旁路控制操作数提取
公开(公告)号：US4189770A
公开(公告)日：1980-02-19
申请号：US887097
申请日：1978-03-16
申请人： Patrick M. Gannon , John S. Liptay
发明人： Patrick M. Gannon , John S. Liptay
IPC分类号： G06F9/308 , G06F9/312 , G06F9/34 , G06F9/38 , G06F12/04 , G06F12/08 , G06F1/00
CPC分类号： G06F9/30018 , G06F12/04 , G06F12/0859 , G06F12/0886 , G06F9/30043 , G06F9/383
摘要： In the case of a cache miss, the successive fetch requests by the I-unit for sublines (e.g. doublewords) of a variable length field operand are provided by the first through the highest-address fetched sublines in a line being accessed from main storage via a cache bypass. This avoids the time delay for the I-unit caused by waiting until the complete line has been transferred to the cache before all required sublines in the line are obtainable from the cache. Address operand pairs (AOP's) consisting of request and buffer registers are provided in the I-unit to handle the fetched sublines as fast as the cache bypass can provide them from main storage. If there is a cache hit, the sublines are accessed from the cache.
摘要翻译：在高速缓存未命中的情况下，由可变长度字段操作数的子单元（例如双字）的I单元的连续提取请求由从主存储器经由主存储器访问的行中的第一到最高地址获取的子行提供缓存旁路。这避免了在缓存中可以获得所有必需的子线之前等待直到完整的线路传输到缓存器为止导致I单元的时间延迟。在I单元中提供由请求和缓冲寄存器组成的地址操作数对（AOP），以便缓存旁路可以从主存储器提供它们来处理获取的子行。如果有缓存命中，则从高速缓存访问子系统。

7. 发明授权

US4136385A Synonym control means for multiple virtual storage systems 失效
标题翻译：用于多个虚拟存储系统的协同控制手段
公开(公告)号：US4136385A
公开(公告)日：1979-01-23
申请号：US781022
申请日：1977-03-24
申请人： Patrick M. Gannon , Andrew R. Heller , Ronald M. Smith
发明人： Patrick M. Gannon , Andrew R. Heller , Ronald M. Smith
IPC分类号： G06F12/10 , G06F13/00
CPC分类号： G06F12/1036
摘要： The embodiments relate to special controls in a processor which eliminate synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual addresses in multiple address spaces into real main storage addresses. The controls provide a common space bit in any segment table entry (STE) or alternatively in any page table entry (PTE) in any private address space to indicate whether the segment or page, respectively, contains programs and data private to the address space or shared by all address spaces. Each DLAT entry contains a common/private storage indictor which is set to the state of the common space bit in the STE or PTE used in an address translation loaded into the DLAT entry. When the entry is read, the private/common storage indicator controls whether the DLAT can only be used by the address space identified in the DLAT, or by all address spaces.

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