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    • 1. 发明授权
    • Bias filter memory for filtering out unnecessary interrogations of cache
directories in a multiprocessor system
    • 偏置过滤器存储器,用于过滤多处理器系统中缓存目录的不必要询问
    • US4142234A
    • 1979-02-27
    • US855485
    • 1977-11-28
    • Bradford M. BeanKeith N. LangstonRichard L. PartridgeKian-Bon K. Sy
    • Bradford M. BeanKeith N. LangstonRichard L. PartridgeKian-Bon K. Sy
    • G06F12/08G06F12/10G06F13/00G06F15/16
    • G06F12/0808
    • The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage.A filter memory is provided with each BIAS in the MP. The filter memory records the cache block address in each invalidation request transferred to its associated BIAS. The filter memory deletes an address when it is deleted from the cache directory and retains the most recent cache access requests.The filter memory may have one or more registers, or be an array. Invalidation interrogation addresses from each remote processor and from local and/or remote channels are received and compared against each valid address recorded in the filter memory. If they compare unequal, the received address is recorded in the filter memory as a valid address, and it is gated into BIAS to perform a cache interrogation. If equal, the inputted address is prevented from entering the filter memory or the BIAS, so that it cannot cause any cache interrogation. Deletion from the filter memory is done when the associated processor fetches a block of data into its cache. Deletion may be of all entries in the filter memory, or of only a valid entry having an address equal to the block fetch address in a fetch address register (FAR). Deletion may be done by resetting a valid bit with each entry.
    • 所公开的实施例滤除多处理器(MP)系统中的处理器的高速缓存目录的许多不必要的询问,由此减少与每个相关联的处理器的缓冲区无效地址堆栈(BIAS)的所需大小,并且通过允许 它在机器周期期间访问其缓存,在先前的MP被要求无效询问。 当每个通道或处理器向共享主存储器生成存储请求时,可以完成每个远程处理器高速缓存目录的无效询问。
    • 2. 发明授权
    • Technique for performing partial stores in store-thru memory
configuration
    • 在存储器存储器配置中执行部分存储的技术
    • US4157586A
    • 1979-06-05
    • US794323
    • 1977-05-05
    • Patrick M. GannonJulius D. JonesDale M. JunodRichard L. PartridgeThomas R. Wright
    • Patrick M. GannonJulius D. JonesDale M. JunodRichard L. PartridgeThomas R. Wright
    • G06F12/04G06F12/08G06F7/02
    • G06F12/0804
    • This specification relates to performance of partial store operation in a hierarchical memory system which has a buffer store interposed between a processor interrogating the memory system and the main memory of the memory system. Such a partial store operation can be performed on a word of data in the main memory using the buffer store copy of that word of data. The copy of the word of data is read out of the buffer store into a register where it is modified to form a new word by replacing one or more but not all of the bytes in the word of data with bytes supplied by the processor. The new word is then placed in the main memory by performing a full store operation. The problem with performing a partial store operation in this manner is that the copy of the word of data in the buffer store may not be up-to-date. A technique is provided to eliminate the possibility of this old data being rewritten back into the main memory.
    • 本说明书涉及在分层存储器系统中的部分存储操作的性能,其具有插入在询问存储器系统的处理器和存储器系统的主存储器之间的缓冲存储器。 可以使用该数据字的缓冲存储副本对主存储器中的数据字执行这种部分存储操作。 将数据字的副本从缓冲存储器中读出到寄存器中,在该寄存器中,通过用处理器提供的字节替换数据字中的一个或多个但不是全部的字节来修改它来形成新的字。 然后通过执行完整的存储操作将新的字放置在主存储器中。 以这种方式执行部分存储操作的问题是缓冲存储器中的数据字的副本可能不是最新的。 提供了一种技术来消除将旧数据重写回主存储器的可能性。