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    • 1. 发明授权
    • High speed store request processing control
    • 高速存储请求处理控制
    • US4149245A
    • 1979-04-10
    • US805065
    • 1977-06-09
    • Patrick M. GannonKian-Bon K. Sy
    • Patrick M. GannonKian-Bon K. Sy
    • G06F12/08G06F9/34G06F12/00G06F12/06G06F13/16G06F13/06G06F9/18
    • G06F13/161
    • The described embodiment provides storage control (PSCF) for overlapping the handling of processor store requests between their generation by an instruction execution means (IPPF) and their presentation to system main storage (MS).The embodiment uses a store counter, an inpointer counter, an outpointer counter, a translator pointer register, an output counter and a plurality of registers sets to process and control the sequencing of all store requests so that the PSCF can output them to MS in the order received from the IPPF. The embodiment uses the counters to coordinate the varying delays in PSCF processing of plural store request contained in different register sets and the translator.The store counter obtains independence between plural IPPF operand address (OA) registers which send the store requests and plural PSCF register sets which handle the store request. The number of OA registers is made independent of the number of register sets. The store counter is also used for serializing instruction control.
    • 所描述的实施例提供了存储控制(PSCF),用于通过指令执行装置(IPPF)及其对系统主存储(MS)的呈现之间的处理来重叠处理器存储请求的处理。
    • 5. 发明授权
    • Routing mechanism with encapsulated FCS for a multi-ring local area
network
    • 用于多环局域网的封装FCS的路由机制
    • US4577313A
    • 1986-03-18
    • US616754
    • 1984-06-04
    • Kian-Bon K. Sy
    • Kian-Bon K. Sy
    • H04L1/00H04L12/46H04J3/00
    • H04L12/4637H04L1/0083H04L12/462H04L2212/00
    • A method and apparatus for protecting the integrity of data in a multi-loop communication network is disclosed. A source station generates and forwards a frame with a unique format and a frame check sequence (FCS). At each bridge, an algorithm is provided to process the frame. If the frame is at a source bridge and not discarded, the FCS is preserved by encapsulating it in the Information field. The source bridge generates a new FCS, appends it to the frame and forwards the frame. Thereafter, each intermediate bridge generates its own FCS, appends it to the frame and forwards the frame. At the target bridge, no FCS is generated. The preserved FCS is forwarded as the FCS of the frame.
    • 公开了一种用于保护多环通信网络中数据完整性的方法和装置。 源站产生并转发具有唯一格式和帧校验序列(FCS)的帧。 在每个网桥上,提供了一种处理帧的算法。 如果帧位于源网桥并且不被丢弃,则FCS通过将其封装在信息字段中而被保留。 源桥生成新的FCS,将其附加到帧并转发帧。 此后,每个中间桥产生自己的FCS,将其附加到帧并转发帧。 在目标桥上,不产生FCS。 保留的FCS作为帧的FCS转发。
    • 8. 发明授权
    • System and method for providing SVC service through an ATM network for
frame relay DTEs with a terminal adapter
    • 通过ATM网络提供带有终端适配器的帧中继DTE的SVC服务的系统和方法
    • US5490141A
    • 1996-02-06
    • US316675
    • 1994-09-30
    • Fuyung LaiKian-Bon K. Sy
    • Fuyung LaiKian-Bon K. Sy
    • H04L12/56H04Q11/04
    • H04Q11/0478H04L2012/5615H04L2012/563H04L2012/564H04L2012/5645H04L2012/5652
    • The system and method of the present invention provide a seamless approach for providing ATM connectivity for a Frame Relay DTE using an intelligent Terminal Adapter (TA). Using the system and method of the present invention, an enhanced Frame Relay protocol runs between the DTE and the ATM TA, the Frame Relay DTE is provided with not only the connectivity to the ATM network but also the full advantages of ATM transport mechanism and, in particular, the connectivity through the ATM network using the SVC connection mechanism. Using the system and method of the present invention, a FR DTE may issue commands to the terminal adapter to set of calls, or connections, with other DTEs (FR or ATM). The terminal adapter then communicates with the ATM network and the destination DTE using the ANSI Q.2931 call establishment procedure (using commands such as Call.sub.-- Set-up, Call.sub.-- Accept, and Call.sub.-- Disconnect) to establish an SVC connection between the communicating DTEs. In addition, the FR DTE sends parameters such as quality of service (QOS), peak bandwidth, etc., so that the Frame Relay DTE can send real-time data, image, voice, or video traffics across the ATM network using the less expensive SVC mechanism.
    • 本发明的系统和方法提供了一种使用智能终端适配器(TA)为帧中继DTE提供ATM连接的无缝方法。 使用本发明的系统和方法,增强型帧中继协议在DTE和ATM TA之间运行,帧中继DTE不仅具有与ATM网络的连接性,而且还具有ATM传送机制的全部优点, 特别是通过使用SVC连接机制的ATM网络的连接。 使用本发明的系统和方法,FR DTE可以向终端适配器发出命令以与其他DTE(FR或ATM)建立呼叫或连接。 终端适配器然后使用ANSI Q.2931呼叫建立过程(使用诸如呼叫建立,呼叫接受和呼叫断开等命令)与ATM网络和目的地DTE进行通信,以在通信之间建立SVC连接 DTE。 此外,FR DTE发送诸如服务质量(QOS),峰值带宽等参数,使得帧中继DTE可以使用较少的ATM网络在ATM网络上发送实时数据,图像,语音或视频流量 昂贵的SVC机制。
    • 9. 发明授权
    • Routing architecture for a multi-ring local area network
    • 多环路局域网路由架构
    • US4621362A
    • 1986-11-04
    • US616742
    • 1984-06-04
    • Kian-Bon K. Sy
    • Kian-Bon K. Sy
    • H04L12/46H04J3/00
    • H04L12/4625H04L12/4637
    • The architecture provides a frame format and procedure for routing messages through a single ring or multi-ring communication system. Stations associated with the exchange of messages are located on the single ring or on different rings of the multi-ring communication system. The rings are connected by bridges to form a local area network. The frame format includes a plurality of control bits positioned within a Routing Information (RI) field, a frame control field and a frame status field. Messages are generated and structured in accordance with the frame format. A group of the control bits, in each message, is set with initial values according to the message type. Thus, different messages are characterized by a different sequence of control bit settings. A routing algorithm analyzes the message and depending on the status of the control bits, the message is processed and ultimately switched to its proper destination.
    • 该架构提供了通过单环或多环通信系统路由消息的帧格式和过程。 与消息交换相关联的站位于单环或多环通信系统的不同环上。 环通过桥连接以形成局域网。 帧格式包括位于路由信息(RI)字段内的多个控制比特,帧控制字段和帧状态字段。 消息根据帧格式生成和结构化。 每个消息中的一组控制位根据消息类型设置为初始值。 因此,不同的消息由不同的控制位设置序列表征。 路由算法分析消息,并根据控制位的状态,处理消息并最终切换到其正确的目的地。
    • 10. 发明授权
    • Bias filter memory for filtering out unnecessary interrogations of cache
directories in a multiprocessor system
    • 偏置过滤器存储器,用于过滤多处理器系统中缓存目录的不必要询问
    • US4142234A
    • 1979-02-27
    • US855485
    • 1977-11-28
    • Bradford M. BeanKeith N. LangstonRichard L. PartridgeKian-Bon K. Sy
    • Bradford M. BeanKeith N. LangstonRichard L. PartridgeKian-Bon K. Sy
    • G06F12/08G06F12/10G06F13/00G06F15/16
    • G06F12/0808
    • The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage.A filter memory is provided with each BIAS in the MP. The filter memory records the cache block address in each invalidation request transferred to its associated BIAS. The filter memory deletes an address when it is deleted from the cache directory and retains the most recent cache access requests.The filter memory may have one or more registers, or be an array. Invalidation interrogation addresses from each remote processor and from local and/or remote channels are received and compared against each valid address recorded in the filter memory. If they compare unequal, the received address is recorded in the filter memory as a valid address, and it is gated into BIAS to perform a cache interrogation. If equal, the inputted address is prevented from entering the filter memory or the BIAS, so that it cannot cause any cache interrogation. Deletion from the filter memory is done when the associated processor fetches a block of data into its cache. Deletion may be of all entries in the filter memory, or of only a valid entry having an address equal to the block fetch address in a fetch address register (FAR). Deletion may be done by resetting a valid bit with each entry.
    • 所公开的实施例滤除多处理器(MP)系统中的处理器的高速缓存目录的许多不必要的询问,由此减少与每个相关联的处理器的缓冲区无效地址堆栈(BIAS)的所需大小,并且通过允许 它在机器周期期间访问其缓存,在先前的MP被要求无效询问。 当每个通道或处理器向共享主存储器生成存储请求时,可以完成每个远程处理器高速缓存目录的无效询问。