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1. 发明授权

US09035959B2 Technique to share information among different cache coherency domains 有权
标题翻译：在不同的缓存一致性域之间共享信息的技术
公开(公告)号：US09035959B2
公开(公告)日：2015-05-19
申请号：US12057601
申请日：2008-03-28
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G09G5/36 , G06F12/08 , G06T1/60
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

2. 发明申请

US20140136797A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 审中-公开
标题翻译：在不同的高速缓存域中分享信息的技术
公开(公告)号：US20140136797A1
公开(公告)日：2014-05-15
申请号：US14158865
申请日：2014-01-20
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

3. 发明申请

US20130117509A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 有权
公开(公告)号：US20130117509A1
公开(公告)日：2013-05-09
申请号：US13722440
申请日：2012-12-20
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

4. 发明申请

US20060143402A1 Mechanism for processing uncacheable streaming data 审中-公开
标题翻译：处理不可流水的数据流的机制
公开(公告)号：US20060143402A1
公开(公告)日：2006-06-29
申请号：US11021662
申请日：2004-12-23
申请人： Srinivas Chennupaty , Jack Doweck , Blaise Fanning , Prashant Sethi , Opher Kahn
发明人： Srinivas Chennupaty , Jack Doweck , Blaise Fanning , Prashant Sethi , Opher Kahn
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F9/30043 , G06F9/30087 , G06F9/383 , G06F12/0888
摘要： In one embodiment, a buffer is presented. The buffer comprises a type designator to designate that the buffer is a streaming read buffer, and a plurality of use designators to indicate whether data within the buffer has been used. The data within the buffer is an uncacheable memory type, such as Uncacheable Speculative Write Combining (USWC) memory. Furthermore, in some embodiments, the buffer is allocated upon execution of a streaming read buffer instruction. In other embodiments, the data within the buffer can only be used once and cannot be cached elsewhere in the processor.
摘要翻译：在一个实施例中，呈现缓冲器。缓冲器包括用于指定缓冲器是流读取缓冲器的类型指示符，以及指示缓冲器内的数据是否已被使用的多个使用指示符。缓冲区中的数据是不可缓存的存储器类型，例如不可缓存的推测写入组合（USWC）存储器。此外，在一些实施例中，在执行流读取缓冲器指令时分配缓冲器。在其他实施例中，缓冲器内的数据只能使用一次，并且不能被缓存在处理器的其他地方。

5. 发明授权

US06662278B1 Adaptive throttling of memory acceses, such as throttling RDRAM accesses in a real-time system 有权
标题翻译：内存访问的自适应调节，例如在实时系统中限制RDRAM访问
公开(公告)号：US06662278B1
公开(公告)日：2003-12-09
申请号：US09667649
申请日：2000-09-22
申请人： Opher Kahn , Erez Birenzwig
发明人： Opher Kahn , Erez Birenzwig
IPC分类号： G06F1200
CPC分类号： G06F1/3275 , G06F1/206 , G06F1/3203 , G06F13/161 , G11C7/04 , G11C7/1006 , G11C7/1072 , G11C7/225 , G11C8/00 , Y02D10/13 , Y02D10/14
摘要： Apparatus and methods to adaptively throttle accesses to memory employ a masking tool to specify the percentage of memory bandwidth available for access. The apparatus applies the mask and monitors the number of memory accesses during a throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window exceeds or is fewer than the percentage of memory bandwidth specified by the mask, access to the memory continues until the end of the throttle-monitoring window. At the end of the throttle-monitoring window, the apparatus selects the next lower mask, which has a lower memory bandwidth allocation, applies the next lower mask, and monitors the number of memory accesses during the next throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window is fewer than the percentage of memory bandwidth specified by the mask, at the end of the throttle-monitoring window, the apparatus selects the next higher mask, which has a higher memory bandwidth allocation, applies the next higher mask, and monitors the number of memory accesses during the next throttle-monitoring window. The mask itself comprises a series of ones and zeros indicating clock cycles where access to memory is allowed or disallowed. The pattern of the mask is designed to minimize the number of clock cycles in which memory is blocked. The apparatus and methods reduce the amount of time that memory is blocked in throttle mode, thus allowing real-time streams to proceed without interruption.
摘要翻译：用于自适应地限制对存储器的访问的装置和方法使用掩蔽工具来指定可用于访问的存储器带宽的百分比。该装置应用掩模并监视节气门监视窗口期间的存储器访问次数。如果节气门监控窗口中的存储器访问次数超过或小于掩码指定的存储器带宽的百分比，则对存储器的访问将持续到油门监视窗口的末尾。在节气门监控窗口的末尾，设备选择具有较低内存带宽分配的下一个下掩码，应用下一个下掩码，并监视下一个油门监视窗口内的存储器访问次数。如果节气门监视窗口内的存储器访问次数小于由掩码指定的存储器带宽的百分比，则在油门监视窗口结束时，设备选择具有较高存储器带宽分配的下一较高掩模，应用下一个更高的掩码，并监视下一个油门监控窗口内的存储器访问次数。掩码本身包括一系列的一个和第零个，表示允许或不允许访问存储器的时钟周期。掩模的图案被设计为最小化存储器被阻塞的时钟周期的数量。该装置和方法减少了在节气门模式下存储器被阻塞的时间量，从而允许实时流不间断地进行。

6. 发明申请

US20090248983A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 有权
标题翻译：在不同的高速缓存域中分享信息的技术
公开(公告)号：US20090248983A1
公开(公告)日：2009-10-01
申请号：US12057601
申请日：2008-03-28
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

7. 发明授权

US07418561B2 Adaptive throttling of memory accesses, such as throttling RDRAM accesses in a real-time system 有权
标题翻译：内存访问的自适应调节，例如在实时系统中限制RDRAM访问
公开(公告)号：US07418561B2
公开(公告)日：2008-08-26
申请号：US10628990
申请日：2003-07-28
申请人： Opher Kahn , Erez Birenzwig
发明人： Opher Kahn , Erez Birenzwig
IPC分类号： G06F13/16
CPC分类号： G06F1/3275 , G06F1/206 , G06F1/3203 , G06F13/161 , G11C7/04 , G11C7/1006 , G11C7/1072 , G11C7/225 , G11C8/00 , Y02D10/13 , Y02D10/14
摘要： Apparatus and methods to adaptively throttle accesses to memory employ a masking tool to specify the percentage of memory bandwidth available for access. The apparatus applies the mask and monitors the number of memory accesses during a throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window exceeds or is fewer than the percentage of memory bandwidth specified by the mask, access to the memory continues until the end of the throttle-monitoring window and at the end of the throttle-monitoring window the apparatus selects the next lower mask for a lower memory bandwidth allocation or selects the next higher mask for a higher memory bandwidth allocation, respectively.
摘要翻译：用于自适应地限制对存储器的访问的装置和方法使用掩蔽工具来指定可用于访问的存储器带宽的百分比。该装置应用掩模并监视节气门监视窗口期间的存储器访问次数。如果节气门监控窗口中的存储器访问次数超过或小于掩码指定的存储器带宽的百分比，则对存储器的访问将持续到油门监控窗口的末尾，并且在油门监控结束时窗口，设备选择下一个较低的存储器带宽分配的下一个掩码，或者分别为更高的存储器带宽分配选择下一个更高的掩码。

8. 发明授权

US07290161B2 Reducing CPU and bus power when running in power-save modes 有权
标题翻译：在省电模式下运行时，降低CPU和总线电源
公开(公告)号：US07290161B2
公开(公告)日：2007-10-30
申请号：US10394256
申请日：2003-03-24
申请人： Opher Kahn
发明人： Opher Kahn
IPC分类号： G06F1/08 , G06F1/32 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/124 , Y02D10/126
摘要： A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.
摘要翻译：处理系统包括总线和处理器，其核心被限制为具有不低于一个或多个总线时钟信号频率中最低的预定倍数的一个或多个核心时钟信号频率。在省电模式下，处理器能够以频率生成一个或多个核心时钟信号，使得最低核心时钟信号频率低于性能模式中的一个或多个总线时钟信号频率中最低的预定倍数。处理器能够通过产生一个或多个总线时钟信号来实现这一点，使得省电模式中的最低总线时钟信号频率低于性能模式下总线时钟信号频率的最低值。

9. 发明授权

US07975161B2 Reducing CPU and bus power when running in power-save modes 有权
标题翻译：在省电模式下运行时，降低CPU和总线电源
公开(公告)号：US07975161B2
公开(公告)日：2011-07-05
申请号：US11906473
申请日：2007-10-02
申请人： Opher Kahn
发明人： Opher Kahn
IPC分类号： G06F1/06 , G06F1/08 , G06F1/04 , G06F1/12
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/124 , Y02D10/126
摘要： A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.
摘要翻译：处理系统包括总线和处理器，其核心被限制为具有不低于一个或多个总线时钟信号频率中最低的预定倍数的一个或多个核心时钟信号频率。在省电模式下，处理器能够以频率生成一个或多个核心时钟信号，使得最低核心时钟信号频率低于性能模式中的一个或多个总线时钟信号频率中最低的预定倍数。处理器能够通过产生一个或多个总线时钟信号来实现这一点，使得省电模式中的最低总线时钟信号频率低于性能模式下总线时钟信号频率的最低值。

10. 发明申请

US20050114628A1 Method and apparatus to support an expanded register set 有权
标题翻译：支持扩展寄存器集的方法和装置
公开(公告)号：US20050114628A1
公开(公告)日：2005-05-26
申请号：US10625240
申请日：2003-07-22
申请人： Opher Kahn , Alexander Peleg , Bob Valentine
发明人： Opher Kahn , Alexander Peleg , Bob Valentine
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30134 , G06F9/30138 , G06F9/30185 , G06F9/34
摘要： Processors and methods having an expanded logical register set. In one embodiment, a processor includes Intel Architecture-32 (IA-32) instruction set decoding logic and an expanded logical register set. The expanded logical register set can include more than eight logical registers of a first type.
摘要翻译：具有扩展逻辑寄存器集的处理器和方法。在一个实施例中，处理器包括Intel架构32（IA-32）指令集解码逻辑和扩展的逻辑寄存器组。扩展逻辑寄存器集可以包括多于八个第一类型的逻辑寄存器。

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