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1. 发明申请

US20050114628A1 Method and apparatus to support an expanded register set 有权
标题翻译：支持扩展寄存器集的方法和装置
公开(公告)号：US20050114628A1
公开(公告)日：2005-05-26
申请号：US10625240
申请日：2003-07-22
申请人： Opher Kahn , Alexander Peleg , Bob Valentine
发明人： Opher Kahn , Alexander Peleg , Bob Valentine
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30134 , G06F9/30138 , G06F9/30185 , G06F9/34
摘要： Processors and methods having an expanded logical register set. In one embodiment, a processor includes Intel Architecture-32 (IA-32) instruction set decoding logic and an expanded logical register set. The expanded logical register set can include more than eight logical registers of a first type.
摘要翻译：具有扩展逻辑寄存器集的处理器和方法。在一个实施例中，处理器包括Intel架构32（IA-32）指令集解码逻辑和扩展的逻辑寄存器组。扩展逻辑寄存器集可以包括多于八个第一类型的逻辑寄存器。

2. 发明授权

US07363476B2 Method and apparatus to support an expanded register set 有权
标题翻译：支持扩展寄存器集的方法和装置
公开(公告)号：US07363476B2
公开(公告)日：2008-04-22
申请号：US10625240
申请日：2003-07-22
申请人： Opher D. Kahn , Alexander Peleg , Bob Valentine
发明人： Opher D. Kahn , Alexander Peleg , Bob Valentine
IPC分类号： G06F9/30 , G06F12/06
CPC分类号： G06F9/30134 , G06F9/30138 , G06F9/30185 , G06F9/34
摘要： According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing mode information. The known IA-32 instruction set is limited to accessing eight logical general integer registers. An IA-32 instruction can specify which of the eight logical general integer registers are to be accessed via 3-bit register identifier fields of the addressing mode information of the instruction. Each 3-bit register identifier can specify any of the eight logical general integer registers. An expanded logical register set (e.g., sixteen logical registers, thirty-two logical registers, sixty-four logical registers, etc.) can be accessed by remapping the addressing mode information to include at least four-bit register identifiers without defining new opcodes or defining additional instruction prefixes.
摘要翻译：根据本发明的实施例，微处理器包括扩展的逻辑寄存器组，其可由包括传统操作码和重新映射的寻址模式信息的指令访问。已知的IA-32指令集仅限于访问8个逻辑通用整数寄存器。 IA-32指令可以通过指令的寻址模式信息的3位寄存器标识符字段来指定8个逻辑通用整数寄存器中的哪一个。每个3位寄存器标识符可以指定八个逻辑通用整数寄存器中的任何一个。扩展的逻辑寄存器组（例如，十六个逻辑寄存器，三十二个逻辑寄存器，六十四个逻辑寄存器等）可以通过重新映射寻址模式信息来包括至少四位寄存器标识符而不定义新的操作码或定义附加指令前缀。

3. 发明授权

US06625724B1 Method and apparatus to support an expanded register set 有权
标题翻译：支持扩展寄存器集的方法和装置
公开(公告)号：US06625724B1
公开(公告)日：2003-09-23
申请号：US09536476
申请日：2000-03-28
申请人： Opher D. Kahn , Alexander Peleg , Bob Valentine
发明人： Opher D. Kahn , Alexander Peleg , Bob Valentine
IPC分类号： G06F930
CPC分类号： G06F9/30134 , G06F9/30138 , G06F9/30185 , G06F9/34
摘要： Processors and methods having an expanded logical register set are disclosed. A processor includes may include Intel Architecture-32 (IA-32) instruction set decoding logic and an expanded logical register set. The expanded logical register set may include more than eight logical registers of a first type. An expanded register set decoding logic, coupled to said IA-32 instruction set decoding logic, may determine that an instruction includes an at least four-bit register identifier, the at least four-bit register identifier to specify one logical register of said expanded logical register set.
摘要翻译：公开了具有扩展逻辑寄存器组的处理器和方法。处理器包括可以包括Intel Architecture-32（IA-32）指令集解码逻辑和扩展逻辑寄存器组。扩展的逻辑寄存器组可以包括多于八个第一类型的逻辑寄存器。耦合到所述IA-32指令集解码逻辑的扩展寄存器组解码逻辑可以确定指令包括至少四位寄存器标识符，所述至少四位寄存器标识符指定所述扩展逻辑的一个逻辑寄存器寄存器集。

4. 发明申请

US20130124834A1 Method and Apparatus for Unpacking Packed Data 有权
公开(公告)号：US20130124834A1
公开(公告)日：2013-05-16
申请号：US13730848
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

5. 发明申请

US20130117538A1 Method and Apparatus for Unpacking Packed Data 有权
公开(公告)号：US20130117538A1
公开(公告)日：2013-05-09
申请号：US13730839
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

6. 发明授权

US08396915B2 Processor for performing multiply-add operations on packed data 失效
公开(公告)号：US08396915B2
公开(公告)日：2013-03-12
申请号：US13603370
申请日：2012-09-04
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

7. 发明申请

US20120198210A1 Microprocessor Having Novel Operations 失效
标题翻译：具有新颖操作的微处理器
公开(公告)号：US20120198210A1
公开(公告)日：2012-08-02
申请号：US13444090
申请日：2012-04-11
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.
摘要翻译：处理器处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。解码器具有控制信号输入。控制信号输入用于接收第一控制信号和第二控制信号。第一控制信号用于指示包装操作。第二控制信号用于指示解封装操作。功能单元耦合到解码器和寄存器。功能单元用于使用第一打包数据执行包操作和拆包操作。处理器还支持移动操作。

8. 发明授权

US07966482B2 Interleaving saturated lower half of data elements from two source registers of packed data 失效
标题翻译：从包装数据的两个源寄存器中交织饱和的下半部分数据元素
公开(公告)号：US07966482B2
公开(公告)日：2011-06-21
申请号：US11451906
申请日：2006-06-12
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/315
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.
摘要翻译：一种装置包括指令解码器，第一和第二源寄存器和耦合到解码器的电路，用于从源寄存器接收压缩数据，并响应于解码器接收到的包指令对压缩数据进行打包。从第一源寄存器接收第一打包数据元素和第二打包数据元素。从第二源寄存器接收第三压缩数据元素和第四打包数据元素。所述电路包装将每个打包数据元素的一部分包装到目的地寄存器中，其结果是来自与来自第一打包数据元素的部分相邻的第二打包数据元素的部分，以及来自与该部分相邻的第四打包数据元素的部分从第三个打包的数据元素。

9. 发明授权

US6128614A Method of sorting numbers to obtain maxima/minima values with ordering 有权
标题翻译：排序数字获得最大/最小值的方法
公开(公告)号：US6128614A
公开(公告)日：2000-10-03
申请号：US246575
申请日：1999-02-08
申请人： Larry Mennemeier , Alexander Peleg , Carole Dulong , Millind Mittal , Benny Eitan , Eiichi Kowashi
发明人： Larry Mennemeier , Alexander Peleg , Carole Dulong , Millind Mittal , Benny Eitan , Eiichi Kowashi
IPC分类号： G06F7/24 , G06F9/30 , G06F9/302 , G06F17/30
CPC分类号： G06F9/30014 , G06F7/24 , G06F9/30021 , G06F9/30036 , Y10S707/99936 , Y10S707/99937
摘要： A technique for sorting packed numbers of two operands into minima or maxima operand with their indices to identify the origin of those selected values. After packing two source operands with a plurality of data elements containing numerical values, greater-than comparison operation is performed on the two operands to generate a mask. The mask is used to identify those corresponding pair of data elements of the first and second operands which need to be passed through the subsequent stages in order to generate a sorted minima or maxima. The operands are AND'ed with the mask or the complement of the mask to generate the required minima/maxima result. The same AND'ing technique is used with two other operands containing indices of the values in the first two operands. The indices identify the originating location of the sorted maxima/minima.
摘要翻译：一种用于将两个操作数的打包数分成最小值或最大值操作数的技术，其索引用于标识这些选定值的起始点。在使用包含数值的多个数据元素打包两个源操作数之后，对两个操作数进行大于比较的操作以生成掩码。掩模用于识别需要通过后续阶段的第一和第二操作数的相应数据元素对，以便生成排序的最小值或最大值。操作数与掩码或掩码的补码进行“和”生成所需的最小/最大值结果。使用与前两个操作数中包含值的两个其他操作数相同的AND'ing技术。这些索引标识了排序最大值/最小值的起始位置。

10. 发明授权

US5666298A Method for performing shift operations on packed data 失效
标题翻译：对打包数据执行移位操作的方法
公开(公告)号：US5666298A
公开(公告)日：1997-09-09
申请号：US701564
申请日：1996-08-22
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F7/00 , G06F5/01 , G06F7/76 , G06F9/30 , G06F9/315 , G06F9/38
CPC分类号： G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
摘要翻译：处理器处理器包括被耦合以接收控制信号的解码器。控制信号具有第一源地址，第二源地址，目的地地址和操作字段。第一个源地址对应于第一个位置。第二源地址对应于第二位置。目的地址对应于第三个位置。操作字段指示将执行一种打包数据移位操作。处理器还包括耦合到解码器的电路。电路用于将存储在第一位置的第一打包数据移位存储在第二位置的值。电路还用于将相应的结果打包数据传送到第三位置。

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