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1. 发明申请

US20130207987A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 审中-公开
公开(公告)号：US20130207987A1
公开(公告)日：2013-08-15
申请号：US13844214
申请日：2013-03-15
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G06T1/60
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

2. 发明申请

US20090248983A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 有权
标题翻译：在不同的高速缓存域中分享信息的技术
公开(公告)号：US20090248983A1
公开(公告)日：2009-10-01
申请号：US12057601
申请日：2008-03-28
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

3. 发明授权

US09035959B2 Technique to share information among different cache coherency domains 有权
标题翻译：在不同的缓存一致性域之间共享信息的技术
公开(公告)号：US09035959B2
公开(公告)日：2015-05-19
申请号：US12057601
申请日：2008-03-28
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G09G5/36 , G06F12/08 , G06T1/60
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

4. 发明授权

US09035960B2 Technique to share information among different cache coherency domains 有权
公开(公告)号：US09035960B2
公开(公告)日：2015-05-19
申请号：US13447279
申请日：2012-04-15
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G09G5/36 , G06F12/08 , G06T1/60
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

5. 发明授权

US08643660B2 Technique to share information among different cache coherency domains 有权
标题翻译：在不同的缓存一致性域之间共享信息的技术
公开(公告)号：US08643660B2
公开(公告)日：2014-02-04
申请号：US13722440
申请日：2012-12-20
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G09G5/36
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

6. 发明申请

US20120200585A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 审中-公开
标题翻译：在不同的高速缓存域中分享信息的技术
公开(公告)号：US20120200585A1
公开(公告)日：2012-08-09
申请号：US13447279
申请日：2012-04-15
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G09G5/36
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

7. 发明申请

US20140136797A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 审中-公开
标题翻译：在不同的高速缓存域中分享信息的技术
公开(公告)号：US20140136797A1
公开(公告)日：2014-05-15
申请号：US14158865
申请日：2014-01-20
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

8. 发明申请

US20130117509A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 有权
公开(公告)号：US20130117509A1
公开(公告)日：2013-05-09
申请号：US13722440
申请日：2012-12-20
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

9. 发明授权

US07975161B2 Reducing CPU and bus power when running in power-save modes 有权
标题翻译：在省电模式下运行时，降低CPU和总线电源
公开(公告)号：US07975161B2
公开(公告)日：2011-07-05
申请号：US11906473
申请日：2007-10-02
申请人： Opher Kahn
发明人： Opher Kahn
IPC分类号： G06F1/06 , G06F1/08 , G06F1/04 , G06F1/12
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/124 , Y02D10/126
摘要： A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.
摘要翻译：处理系统包括总线和处理器，其核心被限制为具有不低于一个或多个总线时钟信号频率中最低的预定倍数的一个或多个核心时钟信号频率。在省电模式下，处理器能够以频率生成一个或多个核心时钟信号，使得最低核心时钟信号频率低于性能模式中的一个或多个总线时钟信号频率中最低的预定倍数。处理器能够通过产生一个或多个总线时钟信号来实现这一点，使得省电模式中的最低总线时钟信号频率低于性能模式下总线时钟信号频率的最低值。

10. 发明申请

US20050114628A1 Method and apparatus to support an expanded register set 有权
标题翻译：支持扩展寄存器集的方法和装置
公开(公告)号：US20050114628A1
公开(公告)日：2005-05-26
申请号：US10625240
申请日：2003-07-22
申请人： Opher Kahn , Alexander Peleg , Bob Valentine
发明人： Opher Kahn , Alexander Peleg , Bob Valentine
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30134 , G06F9/30138 , G06F9/30185 , G06F9/34
摘要： Processors and methods having an expanded logical register set. In one embodiment, a processor includes Intel Architecture-32 (IA-32) instruction set decoding logic and an expanded logical register set. The expanded logical register set can include more than eight logical registers of a first type.
摘要翻译：具有扩展逻辑寄存器集的处理器和方法。在一个实施例中，处理器包括Intel架构32（IA-32）指令集解码逻辑和扩展的逻辑寄存器组。扩展逻辑寄存器集可以包括多于八个第一类型的逻辑寄存器。

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