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1. 发明申请

US20060143402A1 Mechanism for processing uncacheable streaming data 审中-公开
标题翻译：处理不可流水的数据流的机制
公开(公告)号：US20060143402A1
公开(公告)日：2006-06-29
申请号：US11021662
申请日：2004-12-23
申请人： Srinivas Chennupaty , Jack Doweck , Blaise Fanning , Prashant Sethi , Opher Kahn
发明人： Srinivas Chennupaty , Jack Doweck , Blaise Fanning , Prashant Sethi , Opher Kahn
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F9/30043 , G06F9/30087 , G06F9/383 , G06F12/0888
摘要： In one embodiment, a buffer is presented. The buffer comprises a type designator to designate that the buffer is a streaming read buffer, and a plurality of use designators to indicate whether data within the buffer has been used. The data within the buffer is an uncacheable memory type, such as Uncacheable Speculative Write Combining (USWC) memory. Furthermore, in some embodiments, the buffer is allocated upon execution of a streaming read buffer instruction. In other embodiments, the data within the buffer can only be used once and cannot be cached elsewhere in the processor.
摘要翻译：在一个实施例中，呈现缓冲器。缓冲器包括用于指定缓冲器是流读取缓冲器的类型指示符，以及指示缓冲器内的数据是否已被使用的多个使用指示符。缓冲区中的数据是不可缓存的存储器类型，例如不可缓存的推测写入组合（USWC）存储器。此外，在一些实施例中，在执行流读取缓冲器指令时分配缓冲器。在其他实施例中，缓冲器内的数据只能使用一次，并且不能被缓存在处理器的其他地方。

2. 发明授权

US09529708B2 Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software 有权
标题翻译：用于在具有集成存储器控制器的平板计算机的相变存储器内配置分区的装置，其基于来自软件的请求将存储驱动器模拟到存储驱动器
公开(公告)号：US09529708B2
公开(公告)日：2016-12-27
申请号：US13976362
申请日：2011-09-30
申请人： Leena K. Puthiyedath , Blaise Fanning , Toby Opferman , James B. Crossland
发明人： Leena K. Puthiyedath , Blaise Fanning , Toby Opferman , James B. Crossland
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F12/06
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/0631 , G06F3/0643 , G06F3/0644 , G06F12/00 , G06F12/0238 , G06F12/0638 , G06F12/08 , G06F12/0804 , G06F12/0866 , G06F2212/1004 , G06F2212/1056 , G06F2212/2024 , G06F2212/214 , G06F2212/251 , G06F2212/7201
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
摘要翻译：在计算机系统中使用非易失性随机存取存储器（NVRAM）来在平台存储层级中执行多个角色，特别是替换可由I / O访问的传统大容量存储。计算机系统包括执行软件的处理器和耦合到处理器的存储器。存储器的至少一部分包括可由处理器进行字节可重写和字节可擦除的非易失性随机存取存储器（NVRAM）。该系统还包括耦合到NVRAM的存储器控制器，以响应于来自软件的访问大容量存储器的请求来执行存储器访问操作以访问NVRAM。

3. 发明申请

US20140258492A1 AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE 审中-公开
标题翻译：在边界接口中聚合完成信息
公开(公告)号：US20140258492A1
公开(公告)日：2014-09-11
申请号：US14209207
申请日：2014-03-13
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
IPC分类号： H04L12/761
CPC分类号： G06F13/364 , G06F13/385 , G06F13/4265 , G06F15/7807 , G06F15/7825 , G06F2213/0038 , H04L12/28 , H04L12/54 , H04L45/00 , H04L45/16
摘要： In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。然后，路由器可以将聚合完成发送到第一个端点。描述和要求保护其他实施例。

4. 发明授权

US08775700B2 Issuing requests to a fabric 有权
标题翻译：向织物发出请求
公开(公告)号：US08775700B2
公开(公告)日：2014-07-08
申请号：US13248276
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求源代理程序在第一个时钟周期。然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。描述和要求保护其他实施例。

5. 发明授权

US08711875B2 Aggregating completion messages in a sideband interface 有权
标题翻译：在边带接口中聚合完成消息
公开(公告)号：US08711875B2
公开(公告)日：2014-04-29
申请号：US13248243
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
IPC分类号： H04L12/66 , H01L29/06
CPC分类号： G06F13/364 , G06F13/385 , G06F13/4265 , G06F15/7807 , G06F15/7825 , G06F2213/0038 , H04L12/28 , H04L12/54 , H04L45/00 , H04L45/16
摘要： In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。然后，路由器可以将聚合完成发送到第一个端点。描述和要求保护其他实施例。

6. 发明申请

US20130117474A1 GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 有权
公开(公告)号：US20130117474A1
公开(公告)日：2013-05-09
申请号：US13729673
申请日：2012-12-28
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David Lee
IPC分类号： G06F13/38
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.

7. 发明申请

US20130083794A1 Aggregating Completion Messages In A Sideband Interface 有权
标题翻译：边带接口中的聚合完成消息
公开(公告)号：US20130083794A1
公开(公告)日：2013-04-04
申请号：US13248243
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
IPC分类号： H04L12/28 , H04L12/54
CPC分类号： G06F13/364 , G06F13/385 , G06F13/4265 , G06F15/7807 , G06F15/7825 , G06F2213/0038 , H04L12/28 , H04L12/54 , H04L45/00 , H04L45/16
摘要： In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。然后，路由器可以将聚合完成发送到第一个端点。描述和要求保护其他实施例。

8. 发明授权

US07152128B2 General input/output architecture, protocol and related methods to manage data integrity 有权
标题翻译：一般输入/输出架构，协议和相关方法来管理数据完整性
公开(公告)号：US07152128B2
公开(公告)日：2006-12-19
申请号：US10227600
申请日：2002-08-23
申请人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
发明人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
IPC分类号： G06F13/14
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link, validating content of one or more packets embedded within the received datagram, and issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded packets to a transaction layer of the GIO interface. Other embodiments are also described.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。在一个实施例中，描述了一种方法，其包括从通过GIO链路耦合的远程GIO接口在一般输入/输出（GIO）接口处接收数据报，验证嵌入在所接收的数据报中的一个或多个分组的内容，以及向在将嵌入式数据包推送到GIO接口的事务层之前，数据报成功接收数据报的正确验证的远程GIO接口。还描述了其它实施例。

9. 发明授权

US06816986B1 Remapping memory devices during operation 有权
标题翻译：操作期间重映射存储器件
公开(公告)号：US06816986B1
公开(公告)日：2004-11-09
申请号：US09473483
申请日：1999-12-28
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： H02H305
CPC分类号： G06F11/1666 , G06F11/1658 , G06F11/20 , G11C29/76
摘要： According to the invention, systems, apparatus and methods are disclosed for automatically replacing semiconductor based memory in a system while that system is operating. Replacement is accomplished by blocking access to the memory devices to be swapped, copying the contents of the faulty device to the replacement device, swapping the IDs of the two devices, and re-enabling access to the replaced device. This replacement is triggered by interrupts from the error detection logic. After replacement, the system automatically checks the faulty device to determine its suitability for use as a spare in the future. The determination is made by repeatedly writing and reading a pseudo-random pattern into the device and logging any errors.
摘要翻译：根据本发明，公开了系统，装置和方法，用于在系统运行时自动替换系统中的半导体存储器。替换是通过阻止访问要交换的存储设备，将故障设备的内容复制到替换设备，交换两个设备的ID，以及重新启用对更换的设备的访问来实现的。该更换由错误检测逻辑的中断触发。更换后，系统会自动检查故障设备，以确定其将来适合作为备用设备使用。通过重复写入和读取伪随机模式到设备中并记录任何错误来进行确定。

10. 发明授权

US5313577A Translation of virtual addresses in a computer graphics system 失效
标题翻译：在计算机图形系统中翻译虚拟地址
公开(公告)号：US5313577A
公开(公告)日：1994-05-17
申请号：US748357
申请日：1991-08-21
申请人： Kim Meinerth , Colyn Case , Chris Franklin , Blaise Fanning , Rodney Gamache
发明人： Kim Meinerth , Colyn Case , Chris Franklin , Blaise Fanning , Rodney Gamache
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10 , G09G5/06 , G09G5/08 , G09G5/39 , G06F15/00
CPC分类号： G09G5/39 , G06F12/1027 , G06F9/3879 , G09G5/06 , G09G5/08 , G06F12/0831 , G09G2360/121 , G09G2360/127
摘要： A computer graphics processor capable of reading from, and writing to, virtual memory. The invention provides a graphics processing unit which includes, among other things, an graphic processor in the form of an address generator which retrieves data from memory locations, and writes data to memory locations. The address generator retrieves data from memory locations memory access request directly to a memory control unit, which retrieves the contents of the memory location. Prior to issuing the request, the address generator sends the address to a virtual translation unit, which translates the virtual address to a physical address. The virtual translation/FIFO control unit also contains three translation buffers, in which are stored the most recently accessed virtual addresses, which, in many situations, enables the virtual translation/FIFO control unit to translate the virtual address using less memory accesses.
摘要翻译：能够读取和写入虚拟内存的计算机图形处理器。本发明提供了一种图形处理单元，其中包括地址发生器形式的图形处理器，其从存储器位置检索数据，并将数据写入存储单元。地址生成器将存储器存储器访问请求中的数据直接检索到存储器控制单元，存储器控制单元检索存储器位置的内容。在发出请求之前，地址生成器将地址发送到虚拟转换单元，该虚拟转换单元将虚拟地址转换为物理地址。虚拟转换/ FIFO控制单元还包含三个转换缓冲器，其中存储最近访问的虚拟地址，在许多情况下，虚拟转换/ FIFO控制单元能够使用较少的存储器访问来转换虚拟地址。

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