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1. 发明授权

US06634974B2 Chain guide member, a chain guide member manufacturing method and a chain guide member manufacturing apparatus 失效
公开(公告)号：US06634974B2
公开(公告)日：2003-10-21
申请号：US09853030
申请日：2001-05-11
申请人： Akira Fujiwara , Atsushi Shirakawa , Noriaki Matsumoto
发明人： Akira Fujiwara , Atsushi Shirakawa , Noriaki Matsumoto
IPC分类号： F16H708
CPC分类号： B29C45/1639 , B29C45/1704 , F16H7/18 , F16H2007/0872
摘要： A chain guide member used in a chain transmission apparatus, and manufacturing method and apparatus thereof. The chain guide member has a sliding contact section extending along a traveling surface of a chain and coming into sliding contact with the chain, and a reinforcement main body reinforcing and supporting the sliding contact section along the traveling surface of the chain. A part or all of a joint portion between the sliding contact section and the reinforcement main body is joined by melting.

2. 发明授权

US5867436A Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 失效
标题翻译：具有多个放大器组的随机存取存储器，用于在正常和测试模式下进行读写
公开(公告)号：US5867436A
公开(公告)日：1999-02-02
申请号：US803298
申请日：1997-02-20
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译：可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

3. 发明授权

US5636163A Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 失效
标题翻译：具有多个放大器组的随机存取存储器，用于在正常和测试模式下进行读写
公开(公告)号：US5636163A
公开(公告)日：1997-06-03
申请号：US632967
申请日：1996-04-16
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译：可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

4. 发明授权

US5280201A Semiconductor logic circuit apparatus 失效
标题翻译：半导体逻辑电路设备
公开(公告)号：US5280201A
公开(公告)日：1994-01-18
申请号：US760997
申请日：1991-09-17
申请人： Kumiko Fujimori , Hirofumi Shinohara , Noriaki Matsumoto , Shuichi Kato
发明人： Kumiko Fujimori , Hirofumi Shinohara , Noriaki Matsumoto , Shuichi Kato
IPC分类号： G11C11/412 , G11C11/417 , H03K3/356 , H03K19/20 , H03K5/159
CPC分类号： H03K3/356165 , H03K3/356147
摘要： A semiconductor logic circuit apparatus which include a first switching element consisting of a field effect transistor for changing holding data, an inverter circuit whose input is connected with one end of the first switching element, a feedback circuit whose input and output are connected with the output and input of the inverter circuit, and a second switching element connected between the output of the feedback circuit and first or second potential. The second switching element is effective for enabling and disabling the feedback circuit.The first and second switching elements are opened/closed in reverse phase to each other. Feedback of the feedback circuit is prevented until the inverter circuit is driven from its "0" to its "1" holding state, so that driving of the inverter circuit becomes easy and operational stability and operating speed are enhanced.
摘要翻译：一种半导体逻辑电路装置，包括由用于改变保持数据的场效应晶体管组成的第一开关元件，其输入端与第一开关元件的一端连接的反相器电路，其输入和输出与输出端连接的反馈电路逆变器电路的输入以及连接在反馈电路的输出与第一或第二电位之间的第二开关元件。第二开关元件对于启用和禁用反馈电路是有效的。第一和第二开关元件以相反的方式彼此打开/关闭。反馈电路的反馈被阻止，直到逆变器电路从其“0”驱动到“1”保持状态，使得逆变器电路的驱动变得容易，并且提高了操作稳定性和操作速度。

5. 发明授权

US4849938A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4849938A
公开(公告)日：1989-07-18
申请号：US76401
申请日：1987-07-22
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G11C11/408 , G11C29/00 , G11C29/04
CPC分类号： G11C29/844
摘要： In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. A line decoder is responsive to the input address for selecting one of the lines of the normal memory cells, and is inactivated by the output of the comparator when the input address is found to coincide with the programmed address. An input address to the line decoder is applied before the same input address is applied to the comparator.
摘要翻译：在具有主存储单元的行（行或列）和响应于缺陷行的地址而替代缺陷行的备用存储单元的行的冗余配置的半导体存储器件中，比较器将输入到存储器件，其中已经编程的缺陷线的地址，并且当发现输入地址与编程地址一致时，备用线选择器选择备用线。行解码器响应于输入地址以选择正常存储器单元的一行，并且当发现输入地址与编程地址一致时，比较器的输出被非激活。在将相同的输入地址应用于比较器之前，施加到线路解码器的输入地址。

6. 发明授权

US4833653A Dynamic random access memory having selectively activated subarrays 失效
标题翻译：具有选择性激活的子阵列的动态随机存取存储器
公开(公告)号：US4833653A
公开(公告)日：1989-05-23
申请号：US94642
申请日：1987-09-09
申请人： Koichiro Mashiko , Kazutami Arimoto , Kiyohiro Furutani , Noriaki Matsumoto , Yoshio Matsuda
发明人： Koichiro Mashiko , Kazutami Arimoto , Kiyohiro Furutani , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C11/4097
摘要： A DRAM of a partially activating system, in which, in an active cycle, sense amplifiers (91a, 91b) are inactivated and the potential on each pair of bit lines (BLA1, BLA1, BLA2, BLA2) is equalized early in the active cycle only for a subarray to be accessed while the potential is not equalized and the sense amplifiers are kept to be activated for a subarray not to be accessed. At the time of an inactive cycle, all the sense amplifiers (91a, 91b) are activated, and the bit lines (BLA1, BLA1, BLA2, BLA2) in the memory cell array are at an "H" or "L" level depending on information read out in the previous active cycle.
摘要翻译：部分激活系统的DRAM，其中在有效周期中，感测放大器（91a，91b）被去激活，并且每对位线（BLA1，＆amp; B，BA2，＆amp; B＆B）上的电位在只有当电位不均衡时才对待访问的子阵列进行有效周期，并且为不被访问的子阵列保持激活读出放大器。在非活动周期时，所有读出放大器（91a，91b）都被激活，并且存储单元阵列中的位线（BLA1，＆amp; B，B，BLA2，＆UPBALB和B）处于“H”或“L” 取决于在上一个活动周期中读出的信息。

7. 发明授权

US06182707B2 Hollow tubular body for air intake duct, mold therefor, and method of molding the same 失效
标题翻译：用于进气管的空心管体，其模具及其成型方法
公开(公告)号：US06182707B2
公开(公告)日：2001-02-06
申请号：US09284075
申请日：1999-10-12
申请人： Hayato Shiraki , Yoshiaki Sasatani , Noriaki Matsumoto
发明人： Hayato Shiraki , Yoshiaki Sasatani , Noriaki Matsumoto
IPC分类号： F16L900
CPC分类号： F02M35/10321 , B29C45/0005 , B29C45/1705 , B29C45/261 , B29C2045/1719 , B29C2045/1723 , F02M35/10157 , F02M35/10347 , F05C2225/08 , Y02T10/144
摘要： A polyamide resin containing reinforcing fiber is dry blended with a polyamide resin containing no or less reinforcing fiber. A polyamide resin containing 15 to 50% by weight of reinforcing fiber thus obtained is used as a material. By using a moving type core having a two-stage structure including a large diameter moving core and a small diameter moving core, a tubular hollow molded body 17 is formed, and redundant portions 18 and 19 are cut and removed.
摘要翻译：含有增强纤维的聚酰胺树脂与不含或不多的增强纤维的聚酰胺树脂干混。使用含有15〜50重量％的如此获得的增强纤维的聚酰胺树脂作为材料。通过使用具有包括大直径移动芯和小直径移动芯的两级结构的移动型芯，形成管状中空成型体17，并且切割和去除冗余部分18和19。

8. 发明授权

US5375088A Random access memory with plurality of amplifier groups 失效
标题翻译：具有多个放大器组的随机存取存储器
公开(公告)号：US5375088A
公开(公告)日：1994-12-20
申请号：US149540
申请日：1993-11-09
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G06F11/267 , G11C7/10 , G11C29/26 , G11C29/38 , G11C7/00
CPC分类号： G11C7/10 , G11C29/26 , G11C29/38 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译：可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。在正常模式和测试模式下，输入数据被施加到连接到块之一的数据总线上，用于在写入期间同时在块中写入。在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

9. 发明授权

US5132930A CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines 失效
标题翻译： CMOS动态存储器件具有选择性地耦合以形成专用于相邻数据位线的读出放大器的多个触发器电路
公开(公告)号：US5132930A
公开(公告)日：1992-07-21
申请号：US577062
申请日：1990-09-04
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is connected through a switch to a first power supply (Vss). Data nodes of a second flip-flop are connected to a second pair of folded bit lines. Its power supply node is connected through a switch to the first power supply (Vss). A power supply node of a third flip-flop is connected through a switch to a second power supply (Vcc). Data nodes of the third flip-flop are coupled through a first pair of transfer gates to the first pair of the folded bit lines, and through a second pair of transfer gates to the second pair of the folded bit lines. Coupling the first to the third flip-flops forms a first sense amplifier and coupling the second to the third flip-flops forms a second sense amplifier.
摘要翻译：在半导体衬底上形成的金属氧化物半导体（MOS）动态中，第一触发器的数据节点连接到第一对折叠位线。其电源节点通过开关连接到第一电源（Vss）。第二触发器的数据节点连接到第二对折叠位线。其电源节点通过开关连接到第一电源（Vss）。第三触发器的电源节点通过开关连接到第二电源（Vcc）。第三触发器的数据节点通过第一对传输门耦合到第一对折叠位线，并通过第二对传输门耦合到第二对折叠位线。耦合第一至第三触发器形成第一读出放大器并且将第二触发器耦合到第三触发器形成第二读出放大器。

10. 发明授权

US5076866A Heat resistant slide member for internal combustion engine 失效
标题翻译：内燃机用耐热滑动构件
公开(公告)号：US5076866A
公开(公告)日：1991-12-31
申请号：US482299
申请日：1990-02-20
申请人： Seiichi Koike , Tomoyoshi Matsuno , Hiroyuki Horimura , Masao Ichikawa , Noriaki Matsumoto , Kazunori Fukizawa
发明人： Seiichi Koike , Tomoyoshi Matsuno , Hiroyuki Horimura , Masao Ichikawa , Noriaki Matsumoto , Kazunori Fukizawa
IPC分类号： C22C21/00 , C22C49/06 , F01L3/02 , F02F7/00
CPC分类号： F02F7/0085 , C22C21/00 , C22C49/06 , F01L3/02 , B22F2998/00 , B22F2998/10 , F05C2253/16 , Y10S428/924 , Y10S428/937 , Y10T29/49306 , Y10T29/49311
摘要： A heat resistant slide member for an internal combustion engine is a plastically worked member formed from a quenched and solidified aluminum alloy, with a metal flow line in a sliding portion thereof set in a sliding direction. The aluminum alloy contains at least one selected from the group consisting of Cr, Fe, Zr and Ti in an amount of 5% or more and 30% by weight or less and has an average diameter of precipitates and crystallizates therein of 50 .mu.m or less and a tensile strength at 300.degree. C. of 18 kg/mm.sup.2 or more.
摘要翻译：用于内燃机的耐热滑动构件是由淬火和固化的铝合金形成的塑性加工构件，其滑动部分中的金属流动线设置在滑动方向。该铝合金含有选自Cr，Fe，Zr和Ti中的至少一种，其含量为5重量％以上且30重量％以下，并且其中的析出物的平均直径和结晶度为50微米， 300℃下的拉伸强度为18kg / mm 2以上。

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