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1. 发明授权

US06156639A Method for manufacturing contact structure 失效
标题翻译：制造接触结构的方法
公开(公告)号：US06156639A
公开(公告)日：2000-12-05
申请号：US116340
申请日：1998-07-16
申请人： Tetsuhiro Fukao , Yoshihiro Kusumi , Hiroshi Miyatake , Nobuo Fujiwara , Shigenori Sakamori , Satoshi Iida
发明人： Tetsuhiro Fukao , Yoshihiro Kusumi , Hiroshi Miyatake , Nobuo Fujiwara , Shigenori Sakamori , Satoshi Iida
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L23/53223 , H01L21/76838 , H01L23/5226 , H01L2924/0002
摘要： Provided are a method for manufacturing contact structure to prevent, in the wire of a borderless structure, erosion in the contact area between the wire and a conductor. An interlayer insulating film (300) having a wire burying hole is formed and a conductor (400) is buried in the hole. Then, a wire layer (500) covering the hole is formed on the interlayer insulating film (300). The wire layer (500) is made so as to have a borderless structure by using a resist (540) as a mask. A barrier metal layer (510) suppresses erosion in the contact area between the conductor (400) and the wire layer (500).
摘要翻译：提供一种用于制造接触结构的方法，以防止无边界结构的电线在导线和导体之间的接触面积中受到侵蚀。形成具有线掩埋孔的层间绝缘膜（300），将导体（400）埋入孔内。然后，在层间绝缘膜（300）上形成覆盖该孔的导线层（500）。通过使用抗蚀剂（540）作为掩模，将导线层（500）制成为具有无边界结构。阻挡金属层（510）抑制导体（400）和导线层（500）之间的接触区域的侵蚀。

2. 发明授权

US5435886A Method of plasma etching 失效
标题翻译：等离子体蚀刻方法
公开(公告)号：US5435886A
公开(公告)日：1995-07-25
申请号：US247405
申请日：1994-05-23
申请人： Nobuo Fujiwara , Takahiro Maruyama , Kenji Kawai , Takahiro Hoshiko
发明人： Nobuo Fujiwara , Takahiro Maruyama , Kenji Kawai , Takahiro Hoshiko
IPC分类号： C23F4/00 , H01J37/02 , H01J37/32 , H01L21/302 , H01L21/3065 , B44C1/22
CPC分类号： H01J37/32623 , H01J37/026 , H01J37/32192 , H01J37/32678 , H01J37/32706 , H01J2237/0044 , H01J2237/3347
摘要： A method of electron cyclotron resonance plasma etching including generating a constant plasma in a gas in a chamber containing a semiconductor wafer by supplying microwave energy to the chamber continuously and applying a pulsed direct current bias to the semiconductor wafer, wherein the pulsed bias has a period substantially equal to a time constant determined by the capacitance of the semiconductor wafer and the resistance of an ion sheath at the surface of the semiconductor wafer.
摘要翻译：一种电子回旋共振等离子体蚀刻方法，其包括通过向所述腔室连续供给微波能量并向所述半导体晶片施加脉冲直流偏压，在包含半导体晶片的腔室中的气体中产生恒定的等离子体，其中所述脉冲偏压具有周期基本上等于由半导体晶片的电容和离子鞘在半导体晶片表面的电阻确定的时间常数。

3. 发明授权

US4982138A Semiconductor wafer treating device utilizing a plasma 失效
标题翻译：利用等离子体的半导体晶片处理装置
公开(公告)号：US4982138A
公开(公告)日：1991-01-01
申请号：US277640
申请日：1988-11-29
申请人： Nobuo Fujiwara , Kenji Kawai , Moriaki Akazawa , Teruo Shibano , Tomoaki Ishida , Kyusaku Nishioka
发明人： Nobuo Fujiwara , Kenji Kawai , Moriaki Akazawa , Teruo Shibano , Tomoaki Ishida , Kyusaku Nishioka
IPC分类号： H01L21/302 , H01J37/32 , H01L21/205 , H01L21/3065 , H01L21/31 , H05H1/46
CPC分类号： H01J37/32678
摘要： A wafer treating device utilizing a plasma generated by a gas discharge caused by electron cyclotron resonance (ECR) includes a wafer treating chamber and a plasma generating chamber, a microwave supply for supplying microwave energy to the plasma generating chamber, and an electromagnetic coil which surrounds the plasma generating chamber to produce a minimum B-field therein. A plasma generated in the plasma generating chamber by electron cyclotron resonance is confined stably therein by the minimum B-field produced by the coil. Thus, the density and stability of the plasma in the plasma generating chamber are enhanced. The plasma in the plasma generating chamber is conveyed to a wafer in the wafer treating chamber along the diverging lines of a magnetic force. Examples of the minimum B-field producing coil include Ioffe bars, a baseball coil and an Yin-yang coil.
摘要翻译：利用由电子回旋共振（ECR）引起的气体放电产生的等离子体的晶片处理装置包括晶片处理室和等离子体发生室，用于向等离子体发生室供给微波能量的微波电源和围绕该等离子体产生室在其中产生最小的B场。通过电子回旋共振在等离子体发生室中产生的等离子体由线圈产生的最小B场稳定地限制在其中。因此，提高等离子体发生室中的等离子体的密度和稳定性。等离子体发生室中的等离子体沿着磁力的发散线被输送到晶片处理室中的晶片。最小B场产生线圈的实例包括Ioffe棒，棒球线圈和阴阳线圈。

4. 发明授权

US4629998A Variable gain equalizer with a mirror circuit having opposite phase relationship between input and output currents 失效
标题翻译：可变增益均衡器，其具有在输入和输出电流之间具有相反相位关系的镜像电路
公开(公告)号：US4629998A
公开(公告)日：1986-12-16
申请号：US667394
申请日：1984-11-02
申请人： Nobuo Fujiwara
发明人： Nobuo Fujiwara
IPC分类号： H03G1/04 , H03H11/24 , H03F3/04 , H03G3/20
CPC分类号： H03G1/04 , H03H11/24
摘要： A variable gain equalizer comprises an equalizing network having an impedance element coupled between an input terminal to which an input voltage is applied and an output terminal. A potentiometer is provided having first and second mutually complementarily variable resistance portions divided by a slidable tap having an inherent contact resistance connected to ground. The first and second portions of the potentiometer are coupled in the equalizing network in series with the impedance element. An inversion type current mirror curcuit causes an input alternating current to flow as a function of the input voltage in the contact resistance of the potentiometer through the first resistance portion and causes an output alternating current of equal amplitude to, but opposite phase to, the input alternating current to flow in the contact resistance through the second resistance portion and impedance element to the output terminal.
摘要翻译：可变增益均衡器包括均衡网络，其具有耦合在施加输入电压的输入端子与输出端子之间的阻抗元件。电位器具有第一和第二相互互补的电阻部分，由具有连接到地的固有接触电阻的可滑动的分接头分开。电位器的第一和第二部分与均衡网络耦合，与阻抗元件串联。反转型电流镜电路使得输入交流电流作为电位器通过第一电阻部分的接触电阻中的输入电压的函数流动，并且产生与输入相等但相反相位的输出交流电交流电流通过第二电阻部分和阻抗元件在接触电阻中流到输出端子。

5. 发明授权

US06822334B2 Semiconductor device having a layered wiring structure with hard mask covering 失效
标题翻译：具有具有硬掩模覆盖层的层状布线结构的半导体器件
公开(公告)号：US06822334B2
公开(公告)日：2004-11-23
申请号：US09756846
申请日：2001-01-10
申请人： Katsunobu Hori , Nobuo Fujiwara , Takashi Watadani , Makoto Nagano
发明人： Katsunobu Hori , Nobuo Fujiwara , Takashi Watadani , Makoto Nagano
IPC分类号： H01L2348
CPC分类号： H01L21/32139 , H01L21/32136 , H01L21/76885
摘要： A hard mask material 2 such as a silicon oxide film is formed on an aluminum alloy film 3. The hard mask material 2 is patterned in the form of a thick film wiring 6, followed by etching the aluminum alloy film 3 to a given depth through the mask. A resist 5 applied to the thin film portion of the aluminum alloy film 3 is patterned in the form of a thin film wiring 7. Etching through the resist 5 and the hard mask material 2 as a mask is effected to form the thick film wiring 6 and the thin film wiring 7 in the same layer.
摘要翻译：在铝合金膜3上形成诸如氧化硅膜的硬掩模材料2.将硬掩模材料2以厚膜布线6的形式图案化，然后将铝合金膜3蚀刻到给定深度通过面具。施加到铝合金膜3的薄膜部分的抗蚀剂5被图案化为薄膜布线7的形式。通过作为掩模的抗蚀剂5和硬掩模材料2进行蚀刻以形成厚膜布线6 和薄膜布线7在同一层中。

6. 发明授权

US06232209B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06232209B1
公开(公告)日：2001-05-15
申请号：US09440568
申请日：1999-11-15
申请人： Nobuo Fujiwara , Takahiro Maruyama , Shigenori Sakamori , Akemi Teratani , Satoshi Ogino , Kazuyuki Ohmi , Yuzo Irie
发明人： Nobuo Fujiwara , Takahiro Maruyama , Shigenori Sakamori , Akemi Teratani , Satoshi Ogino , Kazuyuki Ohmi , Yuzo Irie
IPC分类号： H01L213205
CPC分类号： H01L21/28114 , H01L21/28044 , H01L21/32137 , H01L29/42376 , H01L29/4941
摘要： A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO2 layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.
摘要翻译：栅电极包括多晶硅层，阻挡层和金属层。金属层和阻挡层分别包括例如W和RuO 2层。在形成栅电极时，使用阻挡层和多晶硅层中的至少一个作为蚀刻停止层蚀刻金属层和阻挡层。

7. 发明授权

US5695597A Plasma reaction apparatus 失效
标题翻译：等离子体反应装置
公开(公告)号：US5695597A
公开(公告)日：1997-12-09
申请号：US518609
申请日：1995-08-17
申请人： Nobuo Fujiwara
发明人： Nobuo Fujiwara
IPC分类号： H01J37/32 , H05H1/46 , H05H11/00
CPC分类号： H01J37/32623 , H01J37/3266 , H05H1/46
摘要： Electric field E is generated radially between reaction container and bar-shaped electrode, magnetic field B is formed perpendicular to the electric field, and wafer is disposed perpendicular to magnetic field B. Therefore, the E.times.B drift of plasma generated by magnetron discharge is in the tangential direction of a circle centered at bar-shaped electrode and is parallel to the surface of wafer, whereby maldistribution of plasma in the radial direction is restricted and plasma is distributed uniformly above the main surface of the wafer.
摘要翻译：电场E在反应容器和棒状电极之间径向产生，磁场B垂直于电场形成，晶片垂直于磁场B设置。因此，磁控管放电产生的等离子体的ExB漂移在以棒状电极为中心的圆的切线方向平行于晶片的表面，由此限制等离子体在径向方向上的分布不均匀，等离子体均匀地分布在晶片的主表面上方。

8. 发明授权

US5668041A Method of manufacturing a semiconductor device having a capacitor 失效
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US5668041A
公开(公告)日：1997-09-16
申请号：US632194
申请日：1996-04-15
申请人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
发明人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/04 , H01L27/105 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/3205 , H01L28/40 , H01L28/55 , Y10S257/915 , Y10S438/978
摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
摘要翻译：根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从层间绝缘膜的顶面角到掩埋导电层的表面。因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

9. 发明授权

US5652186A Semiconductor device and a method of manufacturing thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5652186A
公开(公告)日：1997-07-29
申请号：US632195
申请日：1996-04-15
申请人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
发明人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/04 , H01L27/105 , H01L21/00
CPC分类号： H01L27/10852 , H01L21/3205 , H01L28/40 , H01L28/55 , Y10S257/915 , Y10S438/978
摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
摘要翻译：根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从层间绝缘膜的顶面角到掩埋导电层的表面。因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

10. 发明授权

US5304775A Method of etching a wafer having high anisotropy with a plasma gas containing halogens and in inert element 失效
标题翻译：用含有卤素和惰性元素的等离子体气体蚀刻具有高各向异性的晶片的方法
公开(公告)号：US5304775A
公开(公告)日：1994-04-19
申请号：US710988
申请日：1991-06-06
申请人： Nobuo Fujiwara , Kyusaku Nishioka , Teruo Shibano
发明人： Nobuo Fujiwara , Kyusaku Nishioka , Teruo Shibano
IPC分类号： H01L21/3065 , H01L21/311 , H01L21/3213 , B23K9/00
CPC分类号： H01L21/31111 , H01L21/3065 , H01L21/32136 , H01L21/32137
摘要： Fine processing is performed by using gas which contains halogen in such a manner that halogen ions contributing to an etching process and ions of a light element, the mass of which is smaller than that of the halogen ion and which does not react with a semiconductor wafer, are present in a plasma generated due to electron cyclotron resonance. Since energy in the plasma is in inverse proportion to the mass, the disorder motion of the halogen ions having large mass can be restrained. Therefore, the halogen ions can be made perpendicularly incident upon the surface of the semiconductor wafer. Consequently, etching process revealing high anisotropy can be performed.
摘要翻译：通过使用含有卤素的气体，使得有助于蚀刻工艺的卤素离子和轻质元素的离子质量小于卤素离子的离子并且不与半导体晶片反应来进行精细加工存在于由于电子回旋共振而产生的等离子体中。由于等离子体中的能量与质量成反比，所以可以抑制具有大质量的卤素离子的无序运动。因此，卤素离子可以垂直入射在半导体晶片的表面上。因此，可以进行显示高各向异性的蚀刻工艺。

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