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1. 发明授权

US5442213A Semiconductor device with high dielectric capacitor having sidewall spacers 失效
标题翻译：具有高介电电容器的半导体器件具有侧壁间隔物
公开(公告)号：US5442213A
公开(公告)日：1995-08-15
申请号：US255854
申请日：1994-06-07
申请人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
发明人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/04 , H01L27/105 , G11C11/24
CPC分类号： H01L27/10852 , H01L21/3205 , H01L28/40 , H01L28/55 , Y10S257/915 , Y10S438/978
摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
摘要翻译：根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从层间绝缘膜的顶面角到掩埋导电层的表面。因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

2. 发明授权

US5668041A Method of manufacturing a semiconductor device having a capacitor 失效
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US5668041A
公开(公告)日：1997-09-16
申请号：US632194
申请日：1996-04-15
申请人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
发明人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/04 , H01L27/105 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/3205 , H01L28/40 , H01L28/55 , Y10S257/915 , Y10S438/978
摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
摘要翻译：根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从层间绝缘膜的顶面角到掩埋导电层的表面。因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

3. 发明授权

US5652186A Semiconductor device and a method of manufacturing thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5652186A
公开(公告)日：1997-07-29
申请号：US632195
申请日：1996-04-15
申请人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
发明人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/04 , H01L27/105 , H01L21/00
CPC分类号： H01L27/10852 , H01L21/3205 , H01L28/40 , H01L28/55 , Y10S257/915 , Y10S438/978
摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
摘要翻译：根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从层间绝缘膜的顶面角到掩埋导电层的表面。因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

4. 发明授权

US5534458A Method of manufacturing a semiconductor device with high dielectric capacitor having sidewall spacers 失效
标题翻译：具有具有侧壁间隔物的高介电电容器的半导体器件的制造方法
公开(公告)号：US5534458A
公开(公告)日：1996-07-09
申请号：US442925
申请日：1995-05-17
申请人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
发明人： Tomonori Okudaira , Takeharu Kuroiwa , Nobuo Fujiwara , Keiichiro Kashihara
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/04 , H01L27/105 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/3205 , H01L28/40 , H01L28/55 , Y10S257/915 , Y10S438/978
摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
摘要翻译：根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从层间绝缘膜的顶面角到掩埋导电层的表面。因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

5. 发明授权

US08148248B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08148248B2
公开(公告)日：2012-04-03
申请号：US13053733
申请日：2011-03-22
申请人： Toshiaki Tsutsumi , Tomonori Okudaira , Keiichiro Kashihara , Tadashi Yamaguchi
发明人： Toshiaki Tsutsumi , Tomonori Okudaira , Keiichiro Kashihara , Tadashi Yamaguchi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
摘要翻译：提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一层间绝缘膜依次层叠在金属硅化物上。在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

6. 发明申请

US20070077736A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CARRYING OUT ION IMPLANTATION BEFORE SILICIDE PROCESS 有权
标题翻译：制造半导体器件的方法在硅化工艺之前进行离子植入
公开(公告)号：US20070077736A1
公开(公告)日：2007-04-05
申请号：US11537208
申请日：2006-09-29
申请人： Tadashi Yamaguchi , Keiichiro Kashihara , Tomonori Okudaira , Toshiaki Tsutsumi
发明人： Tadashi Yamaguchi , Keiichiro Kashihara , Tomonori Okudaira , Toshiaki Tsutsumi
IPC分类号： H01L21/04
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
摘要翻译：离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为被掩模层覆盖。然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

7. 发明授权

US06078072A Semiconductor device having a capacitor 失效
标题翻译：具有电容器的半导体器件
公开(公告)号：US06078072A
公开(公告)日：2000-06-20
申请号：US73834
申请日：1998-05-06
申请人： Tomonori Okudaira , Yoshikazu Tsunemine , Keiichiro Kashihara
发明人： Tomonori Okudaira , Yoshikazu Tsunemine , Keiichiro Kashihara
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/76 , H01L27/108 , H01L29/94 , H01L31/113
CPC分类号： H01L27/10852 , H01L28/60 , H01L28/55
摘要： A lower electrode layer 1 of a capacitor 10 is formed by sputtering performed at a temperature lower than 450.degree. C. in an atmosphere containing oxygen, and thereby the lower electrode layer 1 thus formed contains oxygen. Thereby, a method of manufacturing a semiconductor device having the capacitor can suppress current leak, and can prevent peeling of an electrode.
摘要翻译：电容器10的下电极层1通过在低于450℃的温度下在含氧气氛中进行溅射而形成，由此形成的下电极层1含有氧。因此，制造具有电容器的半导体器件的方法可以抑制电流泄漏，并且可以防止电极的剥离。

8. 发明授权

US5418388A Semiconductor device having a capacitor with an adhesion layer 失效
标题翻译：具有具有粘附层的电容器的半导体器件
公开(公告)号：US5418388A
公开(公告)日：1995-05-23
申请号：US214512
申请日：1994-03-18
申请人： Tomonori Okudaira , Takeharu Kuroiwa
发明人： Tomonori Okudaira , Takeharu Kuroiwa
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/108 , H01L29/78
CPC分类号： H01L28/40 , H01L27/10808
摘要： In a semiconductor device and a method of manufacturing the same, adhesion between a capacitor dielectric film made of material having a high dielectric constant and an interlayer insulating film located thereunder is improved, and a leak current from a capacitor lower electrode is effectively prevented. In the semiconductor device, an adhesion layer (11) made of TiO.sub.2, ZrO.sub.2, Ta.sub.2 O.sub.5, Si.sub.3 N.sub.4 or Al.sub.2 O.sub.3 is interposed between the interlayer insulating film made of a silicon oxide film and the capacitor dielectric film made of material having a high dielectric constant. The adhesion layer improves adhesion between the interlayer insulating film and the capacitor dielectric film.
摘要翻译：在半导体装置及其制造方法中，提高了由介电常数高的材料制成的电容器电介质膜与位于其之下的层间绝缘膜之间的粘附性，有效地防止了来自电容器下电极的泄漏电流。在半导体装置中，由氧化硅膜构成的层间绝缘膜和由介电常数高的材料构成的电容器电介质膜之间插入由TiO 2，ZrO 2，Ta 2 O 5，Si 3 N 4或Al 2 O 3构成的粘合层（11）。粘合层提高了层间绝缘膜和电容器电介质膜之间的粘附性。

9. 发明申请

US20100171183A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CARRYING OUT ION IMPLANTATION BEFORE SILICIDE PROCESS 有权
标题翻译：制造半导体器件的方法在硅化工艺之前进行离子植入
公开(公告)号：US20100171183A1
公开(公告)日：2010-07-08
申请号：US12727334
申请日：2010-03-19
申请人： Tadashi YAMAGUCHI , Keiichiro Kashihara , Tomonori Okudaira , Toshiaki Tsutsumi
发明人： Tadashi YAMAGUCHI , Keiichiro Kashihara , Tomonori Okudaira , Toshiaki Tsutsumi
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
摘要翻译：离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为被掩模层覆盖。然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

10. 发明申请

US20080121950A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080121950A1
公开(公告)日：2008-05-29
申请号：US11771340
申请日：2007-06-29
申请人： Tadashi YAMAGUCHI , Keiichiro Kashihara , Tomonori Okudaira , Toshiaki Tsutsumi
发明人： Tadashi YAMAGUCHI , Keiichiro Kashihara , Tomonori Okudaira , Toshiaki Tsutsumi
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7848
摘要： Even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is realized.The channel length direction of n channel MISFET where the silicide region of nickel or a nickel alloy was formed on the source and the drain is arranged so that it may become parallel to the crystal orientation of a semiconductor substrate. Since it is hard to extend the silicide region of nickel or a nickel alloy in the direction of crystal orientation , even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is obtained.
摘要翻译：即使是在n沟道MISFET的源极和漏极中形成镍或镍合金的硅化物区域的情况，也可以实现OFF泄漏电流容易增加的半导体器件。在源极和漏极上形成镍或镍合金的硅化物区域的n沟道MISFET的沟道长度方向被布置成使其可以平行于半导体衬底的晶体取向<100>。由于难以在晶体取向<100>的方向上延伸镍或镍合金的硅化物区域，所以即使在镍或镍合金的硅化物区域形成在n的源极和漏极中的情况通道MISFET，可以容易地提高OFF漏电流的半导体装置。

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