专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06232209B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06232209B1
公开(公告)日：2001-05-15
申请号：US09440568
申请日：1999-11-15
申请人： Nobuo Fujiwara , Takahiro Maruyama , Shigenori Sakamori , Akemi Teratani , Satoshi Ogino , Kazuyuki Ohmi , Yuzo Irie
发明人： Nobuo Fujiwara , Takahiro Maruyama , Shigenori Sakamori , Akemi Teratani , Satoshi Ogino , Kazuyuki Ohmi , Yuzo Irie
IPC分类号： H01L213205
CPC分类号： H01L21/28114 , H01L21/28044 , H01L21/32137 , H01L29/42376 , H01L29/4941
摘要： A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO2 layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.
摘要翻译：栅电极包括多晶硅层，阻挡层和金属层。金属层和阻挡层分别包括例如W和RuO 2层。在形成栅电极时，使用阻挡层和多晶硅层中的至少一个作为蚀刻停止层蚀刻金属层和阻挡层。

2. 发明授权

US06346482B2 Semiconductor device having an improved contact structure and a manufacturing method thereof 失效
标题翻译：具有改进的接触结构的半导体器件及其制造方法
公开(公告)号：US06346482B2
公开(公告)日：2002-02-12
申请号：US09176878
申请日：1998-10-21
申请人： Junko Matsumoto , Shigenori Sakamori , Akemi Teratani , Yoshihiro Kusumi , Tetsuhiro Fukao , Kazuyuki Ohmi , Kanji Tabaru , Nobuaki Yamanaka
发明人： Junko Matsumoto , Shigenori Sakamori , Akemi Teratani , Yoshihiro Kusumi , Tetsuhiro Fukao , Kazuyuki Ohmi , Kanji Tabaru , Nobuaki Yamanaka
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802
摘要： There is described formation of a contact hole without involvement of damage to an etching stopper film and deterioration of electric characteristics, achieved by means of a self-alignment method. An interlayer oxide film is etched through an opening of a resist mask, and by means of plasma etching through use of a processing gas comprising a mixture of a rare gas and a CF-based gas, thereby tapering a shoulder of the silicon nitride film. Alternatively, a silicon oxide film and a silicon nitride film are continually etched through an opening of the resist mask, by means of plasma etching through use of a CH2F2 gas added to a mixed gas including a rare gas and a C4F8 gas.
摘要翻译：描述了通过自对准方法实现的接触孔的形成，而不涉及对蚀刻阻挡膜的损伤和电特性的劣化。通过抗蚀剂掩模的开口蚀刻层间氧化膜，并且通过使用包含稀有气体和CF基气体的混合物的处理气体的等离子体蚀刻，从而使氮化硅膜的台肩逐渐变细。或者，通过使用添加到包括稀有气体和C 4 F 8气体的混合气体中的CH 2 F 2气体的等离子体蚀刻，通过抗蚀剂掩模的开口，连续蚀刻氧化硅膜和氮化硅膜。

3. 发明授权

US6156152A Plasma processing apparatus 失效
标题翻译：等离子体处理装置
公开(公告)号：US6156152A
公开(公告)日：2000-12-05
申请号：US958986
申请日：1997-10-28
申请人： Satoshi Ogino , Kazumasa Yonekura , Hajime Kimura , Shigenori Sakamori
发明人： Satoshi Ogino , Kazumasa Yonekura , Hajime Kimura , Shigenori Sakamori
IPC分类号： H05H1/46 , H01J37/32 , H01L21/302 , H01L21/3065 , C23F1/02
CPC分类号： H01J37/32192 , H01J37/32678
摘要： Provided is a plasma processing apparatus capable of extending an etching parameter to reduce charge-up shape anomalies in dry etching and to enhance etching performance such as selectivity, uniformity, processability or the like. A microwave is controlled to be modulated in frequency and is introduced into a chamber. An ECR face is moved between two positions according to the frequency of the microwave.
摘要翻译：提供了能够延长蚀刻参数以减少干蚀刻中的充电形状异常并提高诸如选择性，均匀性，可加工性等的蚀刻性能的等离子体处理装置。微波被控制为频率调制并被引入腔室。根据微波的频率，ECR面在两个位置之间移动。

4. 发明授权

US06156639A Method for manufacturing contact structure 失效
标题翻译：制造接触结构的方法
公开(公告)号：US06156639A
公开(公告)日：2000-12-05
申请号：US116340
申请日：1998-07-16
申请人： Tetsuhiro Fukao , Yoshihiro Kusumi , Hiroshi Miyatake , Nobuo Fujiwara , Shigenori Sakamori , Satoshi Iida
发明人： Tetsuhiro Fukao , Yoshihiro Kusumi , Hiroshi Miyatake , Nobuo Fujiwara , Shigenori Sakamori , Satoshi Iida
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L23/53223 , H01L21/76838 , H01L23/5226 , H01L2924/0002
摘要： Provided are a method for manufacturing contact structure to prevent, in the wire of a borderless structure, erosion in the contact area between the wire and a conductor. An interlayer insulating film (300) having a wire burying hole is formed and a conductor (400) is buried in the hole. Then, a wire layer (500) covering the hole is formed on the interlayer insulating film (300). The wire layer (500) is made so as to have a borderless structure by using a resist (540) as a mask. A barrier metal layer (510) suppresses erosion in the contact area between the conductor (400) and the wire layer (500).
摘要翻译：提供一种用于制造接触结构的方法，以防止无边界结构的电线在导线和导体之间的接触面积中受到侵蚀。形成具有线掩埋孔的层间绝缘膜（300），将导体（400）埋入孔内。然后，在层间绝缘膜（300）上形成覆盖该孔的导线层（500）。通过使用抗蚀剂（540）作为掩模，将导线层（500）制成为具有无边界结构。阻挡金属层（510）抑制导体（400）和导线层（500）之间的接触区域的侵蚀。

5. 发明授权

US5877081A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5877081A
公开(公告)日：1999-03-02
申请号：US843189
申请日：1997-04-14
申请人： Junko Matsumoto , Shigenori Sakamori
发明人： Junko Matsumoto , Shigenori Sakamori
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/60 , H01L21/768 , H01L23/485 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/31144 , H01L21/76802 , H01L23/485 , H01L2924/0002 , Y10S438/952
摘要： According to this invention, an etching stopper film constituted by a silicon nitride film is stacked on an insulating film constituted by a silicon oxide film for protecting a wiring to prevent damage to the wiring caused by anisotropic dry etching for forming a contact hole. A resist pattern having the same shape as that of the contact hole is formed by using a reflection prevention film containing nitrogen atoms, the etching stopper film and the reflection prevention film in a contact hole formation region which contain nitrogen atoms and have equal selectivity ratios under a predetermined condition are simultaneously removed by etching, so that a semiconductor device having stable performance and simple manufacturing steps can be obtained.
摘要翻译：根据本发明，由氮化硅膜构成的蚀刻阻挡膜层叠在由用于保护布线的氧化硅膜构成的绝缘膜上，以防止由用于形成接触孔的各向异性干蚀刻引起的布线的损坏。具有与接触孔相同形状的抗蚀剂图案通过在包含氮原子的接触孔形成区域中使用含有氮原子的反射防止膜，防蚀蚀膜和防反射膜形成，并且具有相同的选择比通过蚀刻同时去除预定条件，从而可以获得具有稳定性能和简单制造步骤的半导体器件。

6. 发明授权

US06731008B1 Semiconductor device with conductive contact layer structure 失效
标题翻译：具有导电层接触结构的半导体器件
公开(公告)号：US06731008B1
公开(公告)日：2004-05-04
申请号：US08726733
申请日：1996-10-07
申请人： Kazuo Tomita , Shigenori Sakamori , Hiroshi Kimura
发明人： Kazuo Tomita , Shigenori Sakamori , Hiroshi Kimura
IPC分类号： H04L2348
CPC分类号： H01L21/76897 , H01L23/485 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive layer contact structure is provided, in which a contact hole of a diameter smaller than the resolution of photolithography technique is formed in a stabilized manner by an etching with low aspect ratio, the contact resistance regarding a conductive layer formed through this contact hole is low, and the step coverage of the conductive layer is satisfactory such that it is not electrically short-circuited with other conductive layers. A silicon oxide film and a silicon nitride film are formed on a gate electrode as first insulation layers. A silicon oxide film is formed as a second insulation layer having a high etching selectivity with respect to the silicon nitride film provided as an upper insulation layer of the first insulation layer. Reaching a surface of an n+ diffused layer formed at a surface of a silicon substrate as a conductive region, a contact hole is formed. A sidewall spacer is formed at the inner sidewall of the silicon oxide film defining a hole. Due to this sidewall spacer, the contact hole having a diameter smaller than the resolution of photolithography technique is defined by the inner sidewall of the silicon oxide film and silicon nitride film.
摘要翻译：提供了一种导电层接触结构，其中通过低纵横比的蚀刻以稳定的方式形成直径小于光刻技术的分辨率的接触孔，关于通过该接触孔形成的导电层的接触电阻为低，并且导电层的台阶覆盖是令人满意的，使得其不与其它导电层电短路。在栅电极上形成氧化硅膜和氮化硅膜作为第一绝缘层。形成氧化硅膜作为相对于作为第一绝缘层的上绝缘层设置的氮化硅膜具有高蚀刻选择性的第二绝缘层。在形成于硅衬底的表面的n +扩散层的表面作为导电区域形成接触孔。在形成孔的氧化硅膜的内侧壁处形成侧壁间隔物。由于该侧壁间隔物，具有比光刻技术的分辨率小的直径的接触孔由氧化硅膜和氮化硅膜的内侧面限定。

7. 发明授权

US06686269B2 Semiconductor device having improved contact hole structure, and method of manufacturing the same 失效
标题翻译：具有改善的接触孔结构的半导体器件及其制造方法
公开(公告)号：US06686269B2
公开(公告)日：2004-02-03
申请号：US10045009
申请日：2002-01-15
申请人： Shigenori Sakamori
发明人： Shigenori Sakamori
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76829 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Within an interlayer dielectric film laid on a semiconductor substrate, a first conducting line is formed at a position lower than a second conducting line. Further, an etching stopper film, which has an etch selectivity differing from that of the interlayer dielectric films under a certain set of etching conditions, is formed at an intermediate position between the first conducting line and the second conducting line. A contact hole to reach the upper second conducting line is formed by etching under the condition that the interlayer dielectric film has a high etch selectivity with respect to the etching stopper film. The depth of a contact hole is controlled not to reach the lower first conducting line in the event the contact hole is offset from a upper conducting line.
摘要翻译：在位于半导体衬底上的层间电介质膜内，在低于第二导线的位置处形成第一导电线。此外，在第一导电线和第二导线之间的中间位置处形成具有与特定蚀刻条件下的层间绝缘膜的蚀刻选择性不同的蚀刻停止膜。在层间电介质膜相对于蚀刻停止膜具有高蚀刻选择性的条件下，通过蚀刻形成到达第二导电线的接触孔。在接触孔从上导线偏移的情况下，接触孔的深度被控制为不到达下第一导电线。

8. 发明授权

US06638777B2 Apparatus for and method of etching 失效
标题翻译：蚀刻装置和方法
公开(公告)号：US06638777B2
公开(公告)日：2003-10-28
申请号：US10118955
申请日：2002-04-10
申请人： Shigenori Sakamori
发明人： Shigenori Sakamori
IPC分类号： H01L2100
CPC分类号： H01L21/67253
摘要： A film thickness measuring mechanism is provided in an orienter chamber (A or B) or a transport buffer chamber (5) of an etching apparatus. A wafer subjected to a predetermined etching process in an etching chamber (1), for example, is transported temporarily into the orienter chamber (A or B) or the transport buffer chamber (5) in which the film thickness measuring mechanism, in turn, measures an etch depth for the wafer. If the etch depth is out of predetermined tolerance with respect to an etch depth setting, an additional etching process is performed on the wafer. Etch time for the additional etching process is calculated from the actual etch depth measured by the film thickness measuring mechanism, the etch depth setting, and an etch rate of a film to be etched.
摘要翻译：在蚀刻装置的定向室（A或B）或输送缓冲室（5）中设置膜厚测量机构。例如，在蚀刻室（1）中进行预定蚀刻处理的晶片被临时输送到定向室（A或B）或输送缓冲室（5）中，其中膜厚度测量机构测量晶片的蚀刻深度。如果蚀刻深度相对于蚀刻深度设置超出预定公差，则在晶片上执行附加蚀刻工艺。根据由膜厚测量机构测量的实际蚀刻深度，蚀刻深度设置以及要蚀刻的膜的蚀刻速率计算附加蚀刻工艺的蚀刻时间。

9. 发明授权

US06340844B1 Semiconductor device having improved contact hole structure, and method of manufacturing the same 失效
标题翻译：具有改善的接触孔结构的半导体器件及其制造方法
公开(公告)号：US06340844B1
公开(公告)日：2002-01-22
申请号：US09606153
申请日：2000-06-29
申请人： Shigenori Sakamori
发明人： Shigenori Sakamori
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76829 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Within an interlayer dielectric film laid on a semiconductor substrate, a first conducting line is formed at a position lower than a second conducting line. Further, an etching stopper film, which has an etch selectivity differing from that of the interlayer dielectric films under a certain set of etching conditions, is formed at an intermediate position between the first conducting line and the second conducting line. A contact hole to reach the upper second conducting line is formed by etching under the condition that the interlayer dielectric film has a high etch selectivity with respect to the etching stopper film. The depth of a contact hole is controlled not to reach the lower first conducting line in the event the contact hole is offset from a upper conducting line.
摘要翻译：在位于半导体衬底上的层间电介质膜内，在低于第二导线的位置处形成第一导电线。此外，在第一导电线和第二导线之间的中间位置处形成具有与特定蚀刻条件下的层间绝缘膜的蚀刻选择性不同的蚀刻停止膜。在层间电介质膜相对于蚀刻停止膜具有高蚀刻选择性的条件下，通过蚀刻形成到达第二导电线的接触孔。在接触孔从上导线偏移的情况下，接触孔的深度被控制为不到达下第一导电线。

10. 发明授权

US5668052A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5668052A
公开(公告)日：1997-09-16
申请号：US678538
申请日：1996-07-05
申请人： Junko Matsumoto , Shigenori Sakamori
发明人： Junko Matsumoto , Shigenori Sakamori
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/60 , H01L21/768 , H01L23/485 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/31144 , H01L21/76802 , H01L23/485 , H01L2924/0002 , Y10S438/952
摘要： According to this invention, an etching stopper film constituted by a silicon nitride film is stacked on an insulating film constituted by a silicon oxide film for protecting a wiring to prevent damage to the wiring caused by anisotropic dry etching for forming a contact hole. A resist pattern having the same shape as that of the contact hole is formed by using a reflection prevention film containing nitrogen atoms, the etching stopper film and the reflection prevention film in a contact hole formation region which contain nitrogen atoms and have equal selectivity ratios under a predetermined condition are simultaneously removed by etching, so that a semiconductor device having stable performance and simple manufacturing steps can be obtained.
摘要翻译：根据本发明，由氮化硅膜构成的蚀刻阻挡膜层叠在由用于保护布线的氧化硅膜构成的绝缘膜上，以防止由用于形成接触孔的各向异性干蚀刻引起的布线的损坏。具有与接触孔相同形状的抗蚀剂图案通过在包含氮原子的接触孔形成区域中使用含有氮原子的反射防止膜，防蚀蚀膜和防反射膜形成，并且具有相同的选择比通过蚀刻同时去除预定条件，从而可以获得具有稳定性能和简单制造步骤的半导体器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式