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1. 发明申请

US20140070373A1 SEMICONDUCTOR HOLE STRUCTURE 有权
标题翻译：半导体孔结构
公开(公告)号：US20140070373A1
公开(公告)日：2014-03-13
申请号：US13608794
申请日：2012-09-10
申请人： Nien-Yu Tsai , Wei Ming Chen
发明人： Nien-Yu Tsai , Wei Ming Chen
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/31144 , H01L21/76805 , H01L21/76814
摘要： A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer.
摘要翻译：第一电介质层形成在衬底上。在第一电介质层上形成第二电介质层。在第二电介质层中形成第一开口。在第一介电层中形成第二开口。

2. 发明授权

US06410417B1 Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymer 有权
标题翻译：在光致抗蚀剂聚合物的湿剥离过程中形成钨互连和通孔而不发生钨损的方法
公开(公告)号：US06410417B1
公开(公告)日：2002-06-25
申请号：US09186757
申请日：1998-11-05
申请人： Nien-Yu Tsai , Hong-Long Chang , Chun-Wei Chen , Ming-Li Kung
发明人： Nien-Yu Tsai , Hong-Long Chang , Chun-Wei Chen , Ming-Li Kung
IPC分类号： H01L214763
CPC分类号： H01L21/31138
摘要： A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; removing the photoresist layer in an asher using a combination of oxygen plasma and water vapor, the ratio of oxygen plasma and water vapor being less than one; and performing a wet strip on the metal interconnect structure.
摘要翻译：公开了一种在其上形成有多个通孔的电介质层上形成金属互连结构和通孔塞的方法。该方法包括以下步骤：通过多个通孔中的插塞形成钨; 在所述电介质层和所述多个钨通过插塞上沉积金属层; 使用光致抗蚀剂层图案化和蚀刻金属层以形成金属互连结构; 使用氧等离子体和水蒸气的组合去除灰浆中的光致抗蚀剂层，氧等离子体和水蒸汽的比例小于1; 并在金属互连结构上执行湿条。

3. 发明授权

US06306772B1 Deep trench bottle-shaped etching using Cl2 gas 失效
标题翻译：深沟槽瓶形蚀刻使用Cl2气体
公开(公告)号：US06306772B1
公开(公告)日：2001-10-23
申请号：US09552024
申请日：2000-04-19
申请人： Ming-Horng Lin , Ray Lee , Nien-Yu Tsai
发明人： Ming-Horng Lin , Ray Lee , Nien-Yu Tsai
IPC分类号： H01L21302
CPC分类号： H01L21/3081 , H01L21/3065
摘要： A method to fabricate bottle-shaped deep trench into a semiconductor substrate. After a neck profile is formed, the chlorine gas at a predetermined flow rate is added to the etching plasma gas composition, while the flow rates of the plasma gases are increased by about 30% by volume, to create an enlarged lower portion of the deep trench. Preferably, the neck portion is etched using an etching composition which contains HBr, NF3, and (He/O2) provided at flow rates of about 87:13:35 sccm. The enlarged lower portion is etched using an etching composition which contains HBr, NF3, and (He/O2) provided at flow rates of about 113±12:17±2:46±5 sccm, and Cl2 provided at a flow rate between 10 and 40 sccm. It was found that the width of the lower portion of the deep trench can be increased by 100% with minimum side effects such as polymer deposition in the plasma chamber, which could occur as result of substantially increased flow rate of HBr and/or NF3.
摘要翻译：将瓶形深沟槽制造成半导体衬底的方法。在形成颈部轮廓之后，将预定流速的氯气加入到蚀刻等离子体气体组合物中，同时等离子体气体的流量增加约30体积％，以产生深度较大的较低部分沟。优选地，使用包含以约87:13:35sccm的流速提供的HBr，NF 3和（He / O 2）的蚀刻组合物蚀刻颈部。使用包含以约113±12：17±2：46±5sccm的流速提供的HBr，NF 3和（He / O 2）的蚀刻组合物蚀刻扩大的下部，并且以10 和40 sccm。已经发现，深沟槽下部的宽度可以以最小的副作用增加100％，例如等离子体室中的聚合物沉积，这可能由于HBr和/或NF3的流速的显着增加而发生。

4. 发明申请

US20130214424A1 STRUCTURE AND MANUFACTURING METHOD FOR REDUCING STRESS OF CHIP 审中-公开
标题翻译：用于减少芯片应力的结构和制造方法
公开(公告)号：US20130214424A1
公开(公告)日：2013-08-22
申请号：US13535083
申请日：2012-06-27
申请人： Nien-Yu TSAI , Hao YU , Jui-Hung CHIEN , Shih-Chien CHANG
发明人： Nien-Yu TSAI , Hao YU , Jui-Hung CHIEN , Shih-Chien CHANG
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/58 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a structure and a manufacturing method thereof for reducing a stress of a chip. The structure comprises a through-silicon via (TSV), a plurality of reinforcing base and a plurality of base bodies. The reinforcing bases are disposed near and around the TSV. The base bodies are disposed near and around the TSV, and the base is disposed on a side of the reinforcing base. The reinforcing base or the base body does not connected with the TSV.
摘要翻译：本发明提供一种降低芯片应力的结构及其制造方法。该结构包括贯通硅通孔（TSV），多个加强基座和多个基体。加固底座设置在TSV附近和周围。基体在TSV附近和周围设置，并且基部设置在加强基部的一侧。加固基座或基体不与TSV连接。

5. 发明授权

US06998277B2 Method of planarizing spin-on material layer and manufacturing photoresist layer 有权
标题翻译：平面化旋涂材料层和制造光刻胶层的方法
公开(公告)号：US06998277B2
公开(公告)日：2006-02-14
申请号：US10711379
申请日：2004-09-15
申请人： Jefferson Lu , Nien-Yu Tsai , Shu-Ching Yang
发明人： Jefferson Lu , Nien-Yu Tsai , Shu-Ching Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/31058 , H01L21/31138 , H01L21/31144 , H01L21/76808 , H01L22/26 , H01L29/945
摘要： A method of planarizing a spin-on material layer is provided. A substrate having a plurality of openings thereon is provided. A spin-on material layer is formed on the substrate such that the openings are completely filled. A plasma etching process is carried out to remove a portion of the spin-on material layer and expose the substrate surface. During the plasma etching process, the substrate is cooled to maintain an etching selectivity between the spin-on material layer on the substrate surface and the spin-on material layer within the openings so that a planar spin-on material layer is ultimately obtained.
摘要翻译：提供了一种平面化旋涂材料层的方法。提供其上具有多个开口的基板。在基板上形成旋涂材料层，使得开口被完全填充。进行等离子体蚀刻工艺以去除旋涂材料层的一部分并暴露衬底表面。在等离子体蚀刻工艺期间，冷却基板以保持基板表面上的旋涂材料层和开口内的旋涂材料层之间的蚀刻选择性，从而最终获得平面旋涂材料层。

6. 发明授权

US06312983B1 Etching method for reducing bit line coupling in a DRAM 失效
标题翻译：用于减少DRAM中位线耦合的蚀刻方法
公开(公告)号：US06312983B1
公开(公告)日：2001-11-06
申请号：US09426071
申请日：1999-10-21
申请人： Joseph Wu , Chen-Wei Chen , Nien-yu Tsai , J. S. Shiao
发明人： Joseph Wu , Chen-Wei Chen , Nien-yu Tsai , J. S. Shiao
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L21/76804
摘要： A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.
摘要翻译：公开了一种用于形成DRAM存储器阵列的位线的方法。该方法包括以下步骤：在DRAM存储器阵列上形成层间电介质; 蚀刻层间电介质以在层间电介质中形成沟槽，沟槽共同形成位线图案并具有锥形侧壁; 以及将导电材料沉积到沟槽中以形成位线。

7. 发明授权

US6143653A Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss 有权
标题翻译：用钨氧化形成钨互连以防止钨损失的方法
公开(公告)号：US6143653A
公开(公告)日：2000-11-07
申请号：US186303
申请日：1998-10-04
申请人： Nien-Yu Tsai , Hong-Long Chang , Chun-Wei Chen , Ming-Li Kung
发明人： Nien-Yu Tsai , Hong-Long Chang , Chun-Wei Chen , Ming-Li Kung
IPC分类号： H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/31133 , H01L21/76888
摘要： A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; oxidizing the metal interconnect structure and the tungsten via plugs to form a metal oxide layer over the metal interconnect structure and tungsten via plugs; and performing a wet strip on the metal interconnect structure.
摘要翻译：公开了一种在其上形成有多个通孔的电介质层上形成金属互连结构和通孔塞的方法。该方法包括以下步骤：通过多个通孔中的插塞形成钨; 在所述电介质层和所述多个钨通过插塞上沉积金属层; 使用光致抗蚀剂层图案化和蚀刻金属层以形成金属互连结构; 通过插塞氧化金属互连结构和钨，以在金属互连结构和钨通孔上形成金属氧化物层; 并在金属互连结构上执行湿条。

8. 发明申请

US20050196879A1 METHOD OF PLANARIZING SPIN-ON MATERIAL LAYER AND MANUFACTURING PHOTORESIST LAYER 有权
标题翻译：旋转材料层平面化方法
公开(公告)号：US20050196879A1
公开(公告)日：2005-09-08
申请号：US10711379
申请日：2004-09-15
申请人： Jefferson Lu , Nien-Yu Tsai , Shu-Ching Yang
发明人： Jefferson Lu , Nien-Yu Tsai , Shu-Ching Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/31058 , H01L21/31138 , H01L21/31144 , H01L21/76808 , H01L22/26 , H01L29/945
摘要： A method of planarizing a spin-on material layer is provided. A substrate having a plurality of openings thereon is provided. A spin-on material layer is formed on the substrate such that the openings are completely filled. A plasma etching process is carried out to remove a portion of the spin-on material layer and expose the substrate surface. During the plasma etching process, the substrate is cooled to maintain an etching selectivity between the spin-on material layer on the substrate surface and the spin-on material layer within the openings so that a planar spin-on material layer is ultimately obtained.
摘要翻译：提供了一种平面化旋涂材料层的方法。提供其上具有多个开口的基板。在基板上形成旋涂材料层，使得开口被完全填充。进行等离子体蚀刻工艺以去除旋涂材料层的一部分并暴露衬底表面。在等离子体蚀刻工艺期间，冷却基板以保持基板表面上的旋涂材料层和开口内的旋涂材料层之间的蚀刻选择性，从而最终获得平面旋涂材料层。

9. 发明授权

US06743726B2 Method for etching a trench through an anti-reflective coating 有权
标题翻译：通过抗反射涂层蚀刻沟槽的方法
公开(公告)号：US06743726B2
公开(公告)日：2004-06-01
申请号：US10192154
申请日：2002-07-11
申请人： Jefferson Lu , Nien-Yu Tsai
发明人： Jefferson Lu , Nien-Yu Tsai
IPC分类号： H01L21302
CPC分类号： H01L21/76808 , H01L21/0276 , H01L21/31138 , H01L21/31144 , H01L21/76232 , H01L21/76804
摘要： A method for manufacturing a semiconductor device that includes providing a substrate, providing a dielectric layer over the substrate, depositing a layer of anti-reflective coating over the dielectric layer, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, etching the anti-reflective coating to completely remove the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.
摘要翻译：一种用于制造半导体器件的方法，包括提供衬底，在衬底上提供电介质层，在电介质层上沉积抗反射涂层，在抗反射涂层层上提供一层光致抗蚀剂，图案化和限定光致抗蚀剂层以提供多个光致抗蚀剂结构，其中至少两个相邻的光致抗蚀剂结构提供第一距离，各向异性地蚀刻由光致抗蚀剂结构未掩模的抗反射涂层，以仅去除抗反射涂层的一部分，蚀刻抗反射涂层以完全去除由光致抗蚀剂结构未掩蔽的抗反射涂层，并蚀刻介电层以在至少两个相邻的光致抗蚀剂结构之间形成至少一个沟槽，其中第一距离基本相等到在沟槽顶部限定开口的第二距离。

10. 发明授权

US06514817B1 Method of forming shallow trench 有权
标题翻译：形成浅沟槽的方法
公开(公告)号：US06514817B1
公开(公告)日：2003-02-04
申请号：US10116881
申请日：2002-04-05
申请人： Nien-Yu Tsai , Yung-Ching Wang
发明人： Nien-Yu Tsai , Yung-Ching Wang
IPC分类号： H02L218242
CPC分类号： H01L27/1087 , H01L21/76224 , H01L27/10829 , H01L29/66181
摘要： A method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate, each the deep trench capacitor construction having a collar construction and a conductor construction is provided. The method of forming a shallow trench includes steps of (a) defining a mask by forming a mask layer on the semiconductor substrate which has the deep trench capacitor constructions, (b) performing a first etching process with respect to the regions, which is not covered by the mask, so as to form a first depth trench, in which the first etching process has a relatively high selectivity ratio of the conductor construction relative to the mask, and (c) performing a second etching process with respect to the first depth trench so as to form a second depth trench, in which the second etching process has a selectivity ratio of the conductor construction relative to the collar construction substantially close to 1.
摘要翻译：提供了一种在半导体衬底上位于两个相邻的深沟槽电容器结构之间的特定区域中形成浅沟槽的方法，每个深沟槽电容器结构具有套环结构和导体结构。形成浅沟槽的方法包括以下步骤：（a）通过在具有深沟槽电容器结构的半导体衬底上形成掩模层来限定掩模，（b）相对于不是的区域执行第一蚀刻工艺由掩模覆盖，以便形成第一深度沟槽，其中第一蚀刻工艺相对于掩模具有相对高的导体结构选择率，以及（c）相对于第一深度执行第二蚀刻工艺沟槽，以形成第二深度沟槽，其中第二蚀刻工艺具有相对于套环结构的导体结构的选择比基本上接近1。

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