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1. 发明授权

US06312983B1 Etching method for reducing bit line coupling in a DRAM 失效
标题翻译：用于减少DRAM中位线耦合的蚀刻方法
公开(公告)号：US06312983B1
公开(公告)日：2001-11-06
申请号：US09426071
申请日：1999-10-21
申请人： Joseph Wu , Chen-Wei Chen , Nien-yu Tsai , J. S. Shiao
发明人： Joseph Wu , Chen-Wei Chen , Nien-yu Tsai , J. S. Shiao
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L21/76804
摘要： A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.
摘要翻译：公开了一种用于形成DRAM存储器阵列的位线的方法。该方法包括以下步骤：在DRAM存储器阵列上形成层间电介质; 蚀刻层间电介质以在层间电介质中形成沟槽，沟槽共同形成位线图案并具有锥形侧壁; 以及将导电材料沉积到沟槽中以形成位线。

2. 发明授权

US06214713B1 Two step cap nitride deposition for forming gate electrodes 有权
标题翻译：用于形成栅电极的两步骤氮化物沉积
公开(公告)号：US06214713B1
公开(公告)日：2001-04-10
申请号：US09175869
申请日：1998-10-19
申请人： J. S. Shiao
发明人： J. S. Shiao
IPC分类号： H01L2131
CPC分类号： C23C16/345 , H01L21/3185 , Y10S438/902
摘要： A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of polysilicon and a layer of tungsten silicide are sequentially formed on the semiconductor substrate, subsequently, a thin film of silicon nitride is formed at a first temperature and a second silicon nitride is formed at a second temperature, then the pattern of the contact window of gate is defined and the first etching is performed to remove the second and the second silicon nitride, finally, the second etching is performed to remove the layers of polysilicon and tungsten silicide to form a gate electrode.
摘要翻译：一种用于在集成电路中形成栅电极的方法，其中以两步法沉积帽状氮化硅层以改善留在硅化钨表面上的氮化硅残留物的状态。首先，在半导体衬底上依次形成多晶硅层和硅化钨层，随后在第一温度下形成氮化硅薄膜，在第二温度下形成第二氮化硅，限定栅极的接触窗口，并且执行第一蚀刻以去除第二和第二氮化硅，最后，执行第二蚀刻以去除多晶硅层和硅化钨层以形成栅电极。

3. 发明授权

US06110812A Method for forming polycide gate 失效
标题翻译：形成多晶硅栅极的方法
公开(公告)号：US06110812A
公开(公告)日：2000-08-29
申请号：US309934
申请日：1999-05-11
申请人： Chiao-Lin Ho , J. S. Shiao
发明人： Chiao-Lin Ho , J. S. Shiao
IPC分类号： H01L21/28 , H01L29/49 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28061 , H01L29/4933
摘要： A method for forming a polycide-gate structure is disclosed. The method comprises forming a gate oxide layer on a substrate. Then a polysilicon layer is formed on the gate oxide layer. Next a silicide layer is formed over the polysilicon layer. Thereafter, an amorphous silicon layer is formed on the silicide layer. Then, the amorphous silicon layer, the silicide layer, the polysilicon layer and the gate oxide layer are patterned and etched to define a gate region by using a photoresist mask. Source/drain regions are formed using the gate region as an implant mask. Finally, a cap silicon nitride layer is formed over the amorphous silicon layer.
摘要翻译：公开了一种形成多晶硅栅极结构的方法。该方法包括在衬底上形成栅氧化层。然后在栅极氧化物层上形成多晶硅层。接下来，在多晶硅层上形成硅化物层。此后，在硅化物层上形成非晶硅层。然后，通过使用光致抗蚀剂掩模，对非晶硅层，硅化物层，多晶硅层和栅极氧化物层进行图案化和蚀刻以限定栅极区域。使用栅极区域作为植入掩模形成源极/漏极区域。最后，在非晶硅层上形成帽状氮化硅层。

4. 发明授权

US06187650B1 Method for improving global planarization uniformity of a silicon nitride layer used in the formation of trenches by using a sandwich stop layer 有权
标题翻译：通过使用夹心止挡层来改善用于形成沟槽的氮化硅层的全局平坦化均匀性的方法
公开(公告)号：US06187650B1
公开(公告)日：2001-02-13
申请号：US09435334
申请日：1999-11-05
申请人： Joseph Wu , Sheng-Fen Chiu , J. S. Shiao
发明人： Joseph Wu , Sheng-Fen Chiu , J. S. Shiao
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of forming a planar silicon nitride layer is disclosed. The method comprises: forming a pad oxide layer; forming a first nitride layer on the pad oxide layer; forming a stop layer on the first nitride layer; forming a second nitride layer on the stop layer; performing intermediate processes that damage the second nitride layer; removing the second nitride layer; removing the stop layer such that the first nitride layer remains as the planar silicon nitride layer.
摘要翻译：公开了一种形成平面氮化硅层的方法。该方法包括：形成衬垫氧化物层; 在所述焊盘氧化物层上形成第一氮化物层; 在所述第一氮化物层上形成停止层; 在所述停止层上形成第二氮化物层; 执行破坏所述第二氮化物层的中间处理; 去除所述第二氮化物层; 去除停止层，使得第一氮化物层保持为平面氮化硅层。

5. 发明授权

US5393686A Method of forming gate oxide by TLC gettering clean 失效
标题翻译：通过TLC吸附清洁形成栅极氧化物的方法
公开(公告)号：US5393686A
公开(公告)日：1995-02-28
申请号：US297502
申请日：1994-08-29
申请人： Wei-kun Yeh , J. S. Shiao , A. M. Chiang
发明人： Wei-kun Yeh , J. S. Shiao , A. M. Chiang
IPC分类号： H01L21/28 , H01L21/8247 , H01L21/266
CPC分类号： H01L21/28185 , H01L27/11521 , H01L21/28211 , Y10S148/024
摘要： A new method of forming a high quality silicon oxide under a gate electrode for an integrated circuit is described. A gate silicon oxide layer is formed for the gate electrode. A blockout mask is provided for all areas of the integrated circuit not requiring an ion implant. The ion implant is implanted through the gate silicon oxide layer into those areas not covered by the blockout mask. The blockout mask is removed. The gate silicon oxide layer is cleaned to improve the electrical breakdown and charge breakdown characteristics to the state they were before the mask and ion implanting steps by a) treating the gate silicon oxide layer with ammonia and peroxide fluid in the concentration NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=(0.4-1):1:5.5 for between about 3 to 7 minutes at a temperature of between about 60.degree. to 80.degree. C. and b) subjecting the gate silicon oxide layer to an atmosphere of C.sub.2 H.sub.2 Cl.sub.2 and excess oxygen at a temperature of between about 775.degree. to 875.degree. C. for a time of between about 5 to 25 minutes. A polysilicon layer is deposited over the gate silicon oxide layer and patterned to form the gate electrode.
摘要翻译：描述了在用于集成电路的栅电极下形成高质量氧化硅的新方法。为栅电极形成栅氧化硅层。为不需要离子注入的集成电路的所有区域提供阻挡掩模。离子注入通过栅极氧化硅层注入到未被阻挡掩模覆盖的区域中。封堵屏蔽被移除。清洁栅极氧化硅层，以将电击穿和电荷击穿特性改善到其在掩模和离子注入步骤之前的状态，即a）用浓度为NH 4 OH:H 2 O 2 :H 2 O的氨和过氧化物流体处理栅极氧化硅层 =（0.4-1）：1：5.5，在约60〜80℃的温度下约3〜7分钟，b）使栅极氧化硅层在C2H2Cl2和过量氧气的温度下，在约775℃至875℃之间的时间为约5至25分钟。多晶硅层沉积在栅极氧化硅层上并被图案化以形成栅电极。

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