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1. 发明授权

US5706420A Super pipelined speculative execution vector generator 失效
标题翻译：超级流水线推测执行向量生成器
公开(公告)号：US5706420A
公开(公告)日：1998-01-06
申请号：US468608
申请日：1995-06-06
申请人： Monish S. Shah
发明人： Monish S. Shah
IPC分类号： G06F9/38 , G06F7/50 , G06F7/507 , G06T11/20 , G09G1/10 , G06F7/38
CPC分类号： G06F7/507 , G06F2207/3884 , G09G1/10
摘要： A circuit and method for iterative generation of the variables used in vector generation and linear interpolation. Most significant bits are added in a last pipeline stage. Less significant bits are added in earlier pipeline stages. Breaking addition into multiple parts with each part having fewer bits to add enables a faster iterative cycle rate compared to a single long adder. Part of the vector generation algorithm requires a decision step based on the sign of the complete addition. Since this sign is generated in the last stage of the pipeline, it is not available at the time needed by earlier stages of the pipeline. Therefore, all possible combinations of outcomes for earlier pipeline stages are simultaneously speculatively computed for use by following pipeline stages.
摘要翻译：用于迭代生成矢量生成和线性插值中使用的变量的电路和方法。在最后一个流水线阶段添加最高有效位。在较早的流水线阶段增加了不太重要的位。与单个长加法器相比，将每个部分具有较少的位添加到多个部分中可以实现更快的迭代周期速率。矢量生成算法的一部分需要基于完全相加符号的决策步骤。由于该符号是在流水线的最后一个阶段生成的，所以在管道的较早阶段所需的时间内不可用。因此，对于较早的流水线阶段的结果的所有可能组合，同时被推测计算以供以下流水线阶段使用。

2. 发明授权

US5222205A Method for generating addresses to textured graphics primitives stored in rip maps 失效
标题翻译：用于生成地址到RIP MAPS中存储的纹理图形的方法
公开(公告)号：US5222205A
公开(公告)日：1993-06-22
申请号：US494706
申请日：1990-03-16
申请人： Ronald D. Larson , Monish S. Shah
发明人： Ronald D. Larson , Monish S. Shah
IPC分类号： G06T11/20 , G06T15/04
CPC分类号： G06T15/04
摘要： Methods for texture mapping graphics primitives in a graphics pipeline architecture system. The methods utilize rectangular box filters to down-sample original texture maps thereby optimizing aliasing and blurring when graphics primitives have a two-dimensional texture mapped to a three-dimensional object. The methods of texture mapping graphics primitives in a frame buffer graphics system comprise the steps of determining an original texture map of two dimensions for a surface, storing the original texture map in the frame buffer, sampling the original texture map independently using an asymmetrical filter to construct multiple versions of a texture and to address textured pixels on a display in the frame buffer graphics systems, mapping the textured pixels to areas on the frame buffer, and displaying the textured graphics primitives on the display. A technique for addressing textured pixels stored in a rectangular texture (RIP) map is also described.

3. 发明授权

US6108721A Method and apparatus for ensuring data consistency between an i/o channel and a processor 失效
标题翻译：用于确保i / o通道和处理器之间的数据一致性的方法和装置
公开(公告)号：US6108721A
公开(公告)日：2000-08-22
申请号：US107008
申请日：1998-06-29
申请人： William R. Bryg , Monish S. Shah , Thomas V. Spencer
发明人： William R. Bryg , Monish S. Shah , Thomas V. Spencer
IPC分类号： G06F12/08 , G06F13/12 , G06F13/28 , G06F13/38 , G06F13/00
CPC分类号： G06F13/122 , G06F12/0835 , G06F13/28
摘要： In a method and apparatus that ensures data consistency between an I/O channel and a processor, system software issues an instruction which causes the issuance of a transaction when notification of a DMA completion is received. The transaction instructs the I/O channel to enforce coherency and then responds back only after coherency has been ensured. Specifically, a DMA.sub.-- SYNC transaction is broadcast to all I/O channels in the system. Responsive thereto, each I/O channel writes back to memory any modified lines in its cache that might contain DMA data for a DMA sequence that was reported by the system as completed. The I/O channels have a reporting means to indicate when this transaction is completed, so that the DMA.sub.-- SYNC transaction does not have to complete in pipeline order. Thus, the I/O channel can issue new transactions before responding to the DMA.sub.-- SYNC transaction.
摘要翻译：在确保I / O通道与处理器之间的数据一致性的方法和装置中，当接收到DMA完成通知时，系统软件发出导致事务发生的指令。事务指示I / O通道强制执行一致性，然后仅在确保一致性后才响应。具体来说，DMA-SYNC事务被广播到系统中的所有I / O通道。响应于此，每个I / O通道将其缓存中的任何修改的行写回存储器，该行可能包含系统报告的完成的DMA序列的DMA数据。 I / O通道具有报告方式来指示此事务何时完成，以便DMA-SYNC事务不必以流水线顺序完成。因此，在响应DMA-SYNC事务之前，I / O通道可以发出新的事务。

4. 发明授权

US07035981B1 Asynchronous input/output cache having reduced latency 失效
标题翻译：异步输入/输出缓存具有降低的延迟
公开(公告)号：US07035981B1
公开(公告)日：2006-04-25
申请号：US09218333
申请日：1998-12-22
申请人： Thomas V Spencer , Monish S Shah
发明人： Thomas V Spencer , Monish S Shah
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F12/0835 , G06F2212/303
摘要： The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus. In accordance with another aspect of the present invention, a method is provided for buffering or caching data in a shared relationship between a system data bus and an input/output (I/O) data bus, which includes the steps of providing a single data storage area in communication with both a system data bus and an I/O data bus, and providing a single address storage area configured to store system memory addresses corresponding to data contemporaneously stored in the data storage area. In accordance with the broad aspect of the invention, the method further replicates a portion of validation circuitry in both a system frequency domain and an I/O frequency domain. In this way, latency delays encountered when crossing a frequency domain boundary are encountered at times outside a critical path.
摘要翻译：本发明一般涉及包括异步输入/输出（I / O）数据高速缓存的设备。该设备包括与系统数据总线和I / O数据总线通信的单个数据存储区域。类似地，设备包括地址存储区域，其被配置为存储对应于同时存储在数据存储区域中的数据的系统地址。该设备还包括第一电路，其被配置为指示数据存储区域内的数据的有效性状态，用于从I / O数据总线立即访问。类似的第二电路也被包括并且被配置为指示数据存储区域内的数据的有效性状态，用于从系统数据总线的立即访问。根据本发明的另一方面，提供一种用于在系统数据总线和输入/输出（I / O）数据总线之间的共享关系中缓存或缓存数据的方法，其包括以下步骤：提供单个数据存储区域与系统数据总线和I / O数据总线通信，并且提供单个地址存储区域，其被配置为存储对应于同时存储在数据存储区域中的数据的系统存储器地址。根据本发明的广泛方面，该方法进一步复制了系统频域和I / O频域中的一部分验证电路。这样，跨越关键路径的时候会遇到跨越频域边界时遇到的延迟延迟。

5. 发明授权

US5821950A Computer graphics system utilizing parallel processing for enhanced performance 失效
标题翻译：使用并行处理的计算机图形系统提高性能
公开(公告)号：US5821950A
公开(公告)日：1998-10-13
申请号：US634458
申请日：1996-04-18
申请人： Eric M. Rentschler , Monish S. Shah , Mary A. Matthews , Alan S. Krech, Jr. , Erin A. Handgen
发明人： Eric M. Rentschler , Monish S. Shah , Mary A. Matthews , Alan S. Krech, Jr. , Erin A. Handgen
IPC分类号： G06T1/20 , G06T15/00 , G06F15/80
CPC分类号： G06T15/005 , G06T1/20
摘要： A computer graphics system includes a plurality of geometry accelerators for processing vertex data representative of graphics primitives and providing rendering data. The system includes a distributor responsive to a stream of vertex data for distributing to the geometry accelerators chunks of the vertex data for processing by the geometry accelerators to provide chunks of rendering data. The distributor generates an end of chunk bit indicative of the end of each of the chunks of vertex data. The system further includes a concentrator for receiving the chunks of rendering data from each of the geometry accelerators and for combining the chunks of rendering data into a stream of rendering data in response to end of chunk bits. The stream of rendering data and the stream of vertex data represent sequences of graphics primitives having the same order. A rasterizer generates pixel data representative of a graphics display in response to the stream of rendering data.
摘要翻译：计算机图形系统包括多个几何加速器，用于处理表示图形原语的顶点数据并提供呈现数据。该系统包括响应于顶点数据流的分布器，用于分布到几何加速器顶点数据的块中，用于由几何加速器处理以提供重绘数据块。分配器生成指示每个顶点数据块的结束的块位的结尾。该系统还包括一个收集器，用于从每个几何加速器接收渲染数据的块，并且响应于块位的结尾将渲染数据的块组合成渲染数据流。渲染数据流和顶点数据流表示具有相同顺序的图形基元的序列。光栅化器响应于渲染数据流生成表示图形显示的像素数据。

6. 发明授权

US5170468A Graphics system with shadow ram update to the color map 失效
标题翻译：图形系统与影子ram更新到颜色图
公开(公告)号：US5170468A
公开(公告)日：1992-12-08
申请号：US86349
申请日：1987-08-18
申请人： Monish S. Shah , Andrew C. Goris
发明人： Monish S. Shah , Andrew C. Goris
IPC分类号： G06T15/40 , G09G5/06 , G09G5/36 , G09G5/39
CPC分类号： G06T15/405 , G09G5/06 , G09G5/39 , G09G2360/121 , G09G2360/122 , G09G5/363
摘要： A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. A pixel data/partial address multiplexing method based on programmable tile size reduces the number of interconnections between a pixel interpolator and the frame buffer. A programmable pipelined shifter allows the dynamic alteration of the mapping between bits of the RGB intensity values and the planes of the frame buffer into which those bits are stored, as well as allowing those values to be truncated to specified lengths. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache. The Z buffer for hidden surface removal need not be a full size frame buffer, as a lesser portion of frame buffer is, if need be, used repeatedly. Updates to the color map are performed from a separate shadow RAM during vertical retrace. The shadow RAM is large enough to accommodate two copies of the color map, and can load them in automatic alternation, producing a blinking effect without the use of an additional plane of frame buffer memory.
摘要翻译：图形系统使用由帧缓冲存储器组织支持的可编程块大小和形状，其中（X，Y）像素地址映射到RAM地址和数据线分配组上的定期偏移置换。将（X，Y）像素地址更改为组的RAM地址会更改图块的大小和形状。基于可编程块大小的像素数据/部分地址复用方法减少了像素内插器和帧缓冲器之间的互连数量。可编程流水线移位器允许动态改变RGB强度值的位之间的映射以及存储这些位的帧缓冲器的平面，以及允许这些值被截断到指定的长度。瓷砖被缓存。 RGB像素值的瓷砖缓存在RGB缓存中，而Z值缓存在单独的高速缓存中。用于隐藏表面去除的Z缓冲区不需要是全尺寸帧缓冲区，因为如果需要，帧缓冲区的较小部分被重复使用。在垂直回溯期间，从单独的影子RAM执行对颜色映射的更新。影子RAM足够大以容纳彩色地图的两个副本，并且可以自动交替加载它们，从而产生闪烁效果，而不需要使用帧缓冲存储器的附加平面。

7. 发明授权

US06279081B1 System and method for performing memory fetches for an ATM card 有权
标题翻译：用于执行ATM卡的存储器提取的系统和方法
公开(公告)号：US06279081B1
公开(公告)日：2001-08-21
申请号：US09218226
申请日：1998-12-22
申请人： Thomas V Spencer , Robert J Horning , Monish S Shah
发明人： Thomas V Spencer , Robert J Horning , Monish S Shah
IPC分类号： G06F1200
CPC分类号： G06F12/0862
摘要： The present invention is generally directed to a system and method for fetching data from a system memory to an ATM card. The method includes the steps of receiving a request (via a PCI bus) to fetch data from memory, and identifying the request as an ATM request. The method then determines, based on the start address, the number of cache lines that will be implicated by the fetch. Then, the method automatically fetches the appropriate number of cache lines into the cache, and then passes the data to the ATM card, via the PCI bus. In accordance with another aspect of the present invention, a system is provided for fetching data from memory for an ATM card. Broadly, the system includes a system memory for data storage and a cache memory for providing high-speed (retrieval) temporary storage of data, the cache memory being disposed in communication with the system memory via a high-speed system bus. The system further includes a PCI bus in communication with the cache memory via an input/output (I/O) bus. A first mechanism is configured to identify a fetch for data from memory to the PCI bus by an ATM card. A second mechanism is configured to determine the number of lines of the cache memory that will be implicated by the identified fetch. Finally, a third mechanism is configured to automatically fetch the appropriate number of lines from the cache memory and to pass the data to the PCI bus.
摘要翻译：本发明一般涉及一种从系统存储器向ATM卡取出数据的系统和方法。该方法包括以下步骤：通过PCI总线接收从存储器提取数据的请求，并将该请求识别为ATM请求。然后，该方法基于开始地址确定将由提取涉及的高速缓存行的数量。然后，该方法自动将适当数量的高速缓存行提取到高速缓存中，然后通过PCI总线将数据传递到ATM卡。根据本发明的另一方面，提供一种用于从ATM卡的存储器取出数据的系统。广泛地说，该系统包括用于数据存储的系统存储器和用于提供数据的高速（检索）临时存储的高速缓冲存储器，该高速缓冲存储器经由高速系统总线被布置为与系统存储器通信。该系统还包括经由输入/输出（I / O）总线与高速缓冲存储器通信的PCI总线。第一机制被配置为通过ATM卡识别从存储器到PCI总线的数据的提取。第二机制被配置为确定将被识别的提取涉及的高速缓冲存储器的行数。最后，第三种机制被配置为从高速缓冲存储器自动获取适当数量的行并将数据传递到PCI总线。

8. 发明授权

US4958302A Graphics frame buffer with pixel serializing group rotator 失效
标题翻译：具有像素序列化组旋转器的图形帧缓冲器
公开(公告)号：US4958302A
公开(公告)日：1990-09-18
申请号：US86744
申请日：1987-08-18
申请人： Robert W. Fredrickson , Monish S. Shah
发明人： Robert W. Fredrickson , Monish S. Shah
IPC分类号： G09G5/36 , G09G5/39 , G09G5/395
CPC分类号： G09G5/395 , G09G5/39 , G09G2360/121 , G09G2360/122 , G09G5/363
摘要： A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM's. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separated cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput. A group rotator and associated group-sized shift register per bit-plane cooperate during refresh to reorder and serialize the pixels of sixteen by one tiles.
摘要翻译：图形系统使用由帧缓冲存储器组织支持的可编程块大小和形状，其中（X，Y）像素地址映射到RAM地址和数据线分配组上的定期偏移置换。这允许每个组中的一个RAM与每个其他组中的一个RAM一致地与存储器周期一起访问，直到组的数量。在这样的存储循环期间，每个RAM可以接收不同的地址。瓦片是与发送到RAM的地址集合相关联的像素位置的集合。由于排列的规则性质，这些位置可以是由单个边界限定的区域，该边界可以是矩形且具有变化的尺寸和形状。将（X，Y）像素地址更改为组的RAM地址会更改图块的大小和形状。瓷砖被缓存。 RGB像素值的瓷砖缓存在RGB缓存中，而Z值则缓存在分离的高速缓存中。缓存允许局部性的原理将较短的位周期替换到高速缓存用于帧缓冲器的存储器周期，从而提高存储器吞吐量。每个位平面的组旋转器和相关联的组大小的移位寄存器在刷新期间协作以重新排序和序列化16个乘法器的像素。

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