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1. 发明授权

US06279081B1 System and method for performing memory fetches for an ATM card 有权
标题翻译：用于执行ATM卡的存储器提取的系统和方法
公开(公告)号：US06279081B1
公开(公告)日：2001-08-21
申请号：US09218226
申请日：1998-12-22
申请人： Thomas V Spencer , Robert J Horning , Monish S Shah
发明人： Thomas V Spencer , Robert J Horning , Monish S Shah
IPC分类号： G06F1200
CPC分类号： G06F12/0862
摘要： The present invention is generally directed to a system and method for fetching data from a system memory to an ATM card. The method includes the steps of receiving a request (via a PCI bus) to fetch data from memory, and identifying the request as an ATM request. The method then determines, based on the start address, the number of cache lines that will be implicated by the fetch. Then, the method automatically fetches the appropriate number of cache lines into the cache, and then passes the data to the ATM card, via the PCI bus. In accordance with another aspect of the present invention, a system is provided for fetching data from memory for an ATM card. Broadly, the system includes a system memory for data storage and a cache memory for providing high-speed (retrieval) temporary storage of data, the cache memory being disposed in communication with the system memory via a high-speed system bus. The system further includes a PCI bus in communication with the cache memory via an input/output (I/O) bus. A first mechanism is configured to identify a fetch for data from memory to the PCI bus by an ATM card. A second mechanism is configured to determine the number of lines of the cache memory that will be implicated by the identified fetch. Finally, a third mechanism is configured to automatically fetch the appropriate number of lines from the cache memory and to pass the data to the PCI bus.
摘要翻译：本发明一般涉及一种从系统存储器向ATM卡取出数据的系统和方法。该方法包括以下步骤：通过PCI总线接收从存储器提取数据的请求，并将该请求识别为ATM请求。然后，该方法基于开始地址确定将由提取涉及的高速缓存行的数量。然后，该方法自动将适当数量的高速缓存行提取到高速缓存中，然后通过PCI总线将数据传递到ATM卡。根据本发明的另一方面，提供一种用于从ATM卡的存储器取出数据的系统。广泛地说，该系统包括用于数据存储的系统存储器和用于提供数据的高速（检索）临时存储的高速缓冲存储器，该高速缓冲存储器经由高速系统总线被布置为与系统存储器通信。该系统还包括经由输入/输出（I / O）总线与高速缓冲存储器通信的PCI总线。第一机制被配置为通过ATM卡识别从存储器到PCI总线的数据的提取。第二机制被配置为确定将被识别的提取涉及的高速缓冲存储器的行数。最后，第三种机制被配置为从高速缓冲存储器自动获取适当数量的行并将数据传递到PCI总线。

2. 发明授权

US07035981B1 Asynchronous input/output cache having reduced latency 失效
标题翻译：异步输入/输出缓存具有降低的延迟
公开(公告)号：US07035981B1
公开(公告)日：2006-04-25
申请号：US09218333
申请日：1998-12-22
申请人： Thomas V Spencer , Monish S Shah
发明人： Thomas V Spencer , Monish S Shah
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F12/0835 , G06F2212/303
摘要： The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus. In accordance with another aspect of the present invention, a method is provided for buffering or caching data in a shared relationship between a system data bus and an input/output (I/O) data bus, which includes the steps of providing a single data storage area in communication with both a system data bus and an I/O data bus, and providing a single address storage area configured to store system memory addresses corresponding to data contemporaneously stored in the data storage area. In accordance with the broad aspect of the invention, the method further replicates a portion of validation circuitry in both a system frequency domain and an I/O frequency domain. In this way, latency delays encountered when crossing a frequency domain boundary are encountered at times outside a critical path.
摘要翻译：本发明一般涉及包括异步输入/输出（I / O）数据高速缓存的设备。该设备包括与系统数据总线和I / O数据总线通信的单个数据存储区域。类似地，设备包括地址存储区域，其被配置为存储对应于同时存储在数据存储区域中的数据的系统地址。该设备还包括第一电路，其被配置为指示数据存储区域内的数据的有效性状态，用于从I / O数据总线立即访问。类似的第二电路也被包括并且被配置为指示数据存储区域内的数据的有效性状态，用于从系统数据总线的立即访问。根据本发明的另一方面，提供一种用于在系统数据总线和输入/输出（I / O）数据总线之间的共享关系中缓存或缓存数据的方法，其包括以下步骤：提供单个数据存储区域与系统数据总线和I / O数据总线通信，并且提供单个地址存储区域，其被配置为存储对应于同时存储在数据存储区域中的数据的系统存储器地址。根据本发明的广泛方面，该方法进一步复制了系统频域和I / O频域中的一部分验证电路。这样，跨越关键路径的时候会遇到跨越频域边界时遇到的延迟延迟。

3. 发明授权

US06457105B1 System and method for managing data in an asynchronous I/O cache memory 有权
标题翻译：用于管理异步I / O高速缓冲存储器中的数据的系统和方法
公开(公告)号：US06457105B1
公开(公告)日：2002-09-24
申请号：US09232505
申请日：1999-01-15
申请人： Thomas V Spencer , Robert J Horning
发明人： Thomas V Spencer , Robert J Horning
IPC分类号： G06F1200
CPC分类号： G06F12/121 , G06F2212/303
摘要： The present invention is generally directed to a system and method for providing improved memory management in an asynchronous I/O cache memory. The method includes the steps of identifying a request for data from the system memory by a requesting device that is in communication with the system memory via an I/O bus. Then the method controls the communication of data from the system memory into the cache memory. The method further includes the step of communicating the data from the cache memory to the requesting device, and immediately after communicating the data to the requesting device, the method discards the data from the cache memory. In accordance with the preferred embodiment, the method flushes data from the I/O cache line at a time. Therefore, when a given cache line of data is flushed from the cache after the last data byte of the cache line is communicated out to the requesting device.
摘要翻译：本发明一般涉及用于在异步I / O高速缓冲存储器中提供改进的存储器管理的系统和方法。该方法包括以下步骤：通过经由I / O总线与系统存储器通信的请求设备来识别来自系统存储器的数据请求。然后，该方法控制从系统存储器到高速缓冲存储器的数据通信。该方法还包括将数据从高速缓冲存储器传送到请求设备，并且在将数据传送到请求设备之后立即将该数据从高速缓冲存储器中丢弃的步骤。根据优选实施例，该方法一次从I / O高速缓存行刷新数据。因此，当在高速缓存行的最后一个数据字节被传送到请求设备之后，从缓存中刷新给定的高速缓存行数据时。

4. 发明授权

US06542968B1 System and method for managing data in an I/O cache 失效
标题翻译：用于管理I / O缓存中的数据的系统和方法
公开(公告)号：US06542968B1
公开(公告)日：2003-04-01
申请号：US09232293
申请日：1999-01-15
申请人： Thomas V Spencer , Robert J Horning
发明人： Thomas V Spencer , Robert J Horning
IPC分类号： G06F1200
CPC分类号： G06F12/0875 , G06F12/0862 , G06F2212/6028
摘要： The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria. Finally, the system includes a register selector that is configured to select an active register among the plurality of registers, wherein fetching criteria for the device is specified by the active register.
摘要翻译：本发明一般涉及一种系统和方法，用于经由I / O高速缓存将数据从系统存储器提取到与PCI总线通信的设备。概括地说，本发明可以被看作是传达某些提取提示的新颖方式; 即指定要从系统内存中提取的数据的某些质量的提示。在操作中，I / O缓存可以使用这样的提示来更有效地管理通过它的数据。作为一个例子，如果基于提示，I / O缓存的控制器知道（或假设）所取出的数据是ATM数据，则它也将精确地知道（基于ATM数据的性质），将48个字节的数据有效载荷发送到请求设备，并且I / O缓存可以精确地预取这一数量的数据（通常为一个或两个高速缓存行）。根据本发明的一个方面，这种系统包括插入在系统存储器和PCI总线之间的输入/输出（I / O）高速缓冲存储器，其中高速缓冲存储器具有多个数据形式的内部存储器空间高速缓存中的行。该系统还包括用于每个PCI主机的多个寄存器，其被配置为定义提取准则。最后，该系统包括一个寄存器选择器，被配置为在多个寄存器中选择一个活动寄存器，其中由该寄存器指定该设备的取得标准。

5. 发明授权

US06311247B1 System for bridging a system bus with multiple PCI buses 有权
标题翻译：用于桥接具有多条PCI总线的系统总线的系统
公开(公告)号：US06311247B1
公开(公告)日：2001-10-30
申请号：US09232193
申请日：1999-01-15
申请人： Thomas V Spencer
发明人： Thomas V Spencer
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： The present invention is directed to a system for interfacing a system bus to a plurality of Peripheral Component Interconnect (PCI) buses. Specifically, the invention is directed to a system that interfaces a system bus to a plurality of PCI buses, wherein each PCI bus is dedicated to a single PCI device, or slot. The configuration provided by the present invention realizes significant performance enhancements over prior art systems that have shared PCI buses (multiple PCI devices per PCI bus), by providing a direct pipe between the system bus to each PCI device. In accordance with the invention, the system comprises multiple integrated circuit components, including a first integrated circuit and a plurality of second integrated circuit components. The first integrated circuit includes a system bus interface configured to interface with the system bus and a plurality of output interfaces. Each output interface has a fewer number of signals than the system bus interface, and each is configured to generally operate at a communication frequency that matches the communication frequency of a corresponding PCI device/bus. Each of the second integrated circuits includes a PCI interface configured to interface with a PCI bus and at least one input interface configured to directly interface with an output interface of the first integrated circuit.
摘要翻译：本发明涉及一种用于将系统总线连接到多个外围组件互连（PCI）总线的系统。具体地，本发明涉及一种将系统总线与多个PCI总线相接合的系统，其中每个PCI总线专用于单个PCI设备或时隙。本发明提供的配置通过在系统总线与每个PCI设备之间提供直接管道，实现了具有共享PCI总线（每个PCI总线的多个PCI设备）的现有技术系统的显着性能增强。根据本发明，该系统包括多个集成电路部件，包括第一集成电路和多个第二集成电路部件。第一集成电路包括被配置为与系统总线和多个输出接口接口的系统总线接口。每个输出接口具有比系统总线接口少的信号数量，并且每个输出接口被配置为通常以与对应的PCI设备/总线的通信频率相匹配的通信频率工作。每个第二集成电路包括被配置为与PCI总线接口的PCI接口和被配置为直接与第一集成电路的输出接口接口的至少一个输入接口。

6. 发明授权

US06295582B1 System and method for managing data in an asynchronous I/O cache memory to maintain a predetermined amount of storage space that is readily available 有权
标题翻译：用于管理异步I / O高速缓冲存储器中的数据以维持容易获得的预定量的存储空间的系统和方法
公开(公告)号：US06295582B1
公开(公告)日：2001-09-25
申请号：US09232194
申请日：1999-01-15
申请人： Thomas V Spencer
发明人： Thomas V Spencer
IPC分类号： G06F1212
CPC分类号： G06F12/0804 , G06F12/0866 , G06F12/12
摘要： A system and method are described for providing improved cache memory management. Broadly, the system and method improve the performance of an asynchronous input/output (I/O) cache by ensuring that a certain predetermined amount of space is readily available, at all times, to receive new data. In this regard, a memory manager monitors the cache memory space, and evaluates how much “free” or available space exists at all times. As new data is read into the cache memory space, the amount of “free” space is reduced. Once the free spaced is reduced below a predetermined amount, then one or more cache lines are flushed or discarded to ensure that the predetermined amount of space remains available at all times. Significantly, the system and method eliminate the latency that is associated with checking a cache to determine whether free space is available and/or freeing up space in a cache for new data.
摘要翻译：描述了用于提供改进的高速缓存存储器管理的系统和方法。广泛地说，系统和方法通过确保随时可用的某一预定量的空间来接收新的数据来提高异步输入/输出（I / O）缓存的性能。在这方面，存储器管理器监视高速缓存存储器空间，并评估在任何时候存在多少“空闲”或可用空间。随着新数据被读入高速缓冲存储器空间，减少了“空闲”空间的量。一旦空闲间隔减小到预定量以下，则一个或多个高速缓存行被刷新或丢弃，以确保预定量的空间始终保持可用。重要的是，系统和方法消除了与检查缓存相关联的延迟，以确定是否有空闲空间和/或释放高速缓存中的新空间。

7. 发明授权

US6157977A Bus bridge and method for ordering read and write operations in a write posting system 有权
标题翻译：总线桥接器和用于在写入过帐系统中排序读写操作的方法
公开(公告)号：US6157977A
公开(公告)日：2000-12-05
申请号：US198833
申请日：1998-11-24
申请人： Derek A Sherlock , Thomas V Spencer , Francisco Corella
发明人： Derek A Sherlock , Thomas V Spencer , Francisco Corella
IPC分类号： G06F12/08 , G06F13/36 , G06F13/00 , G06F12/00
CPC分类号： G06F12/0835 , G06F2212/306
摘要： A bus bridge is disclosed that provides an interface between two computer buses and guarantees the proper ordering of write operations mastered from one bus relative to read operations mastered from the other bus where the presence of write posting storage in the bus bridge could cause ordering violations. The bus bridge includes a first mechanism for counting the number of write operations that are received by the bus bridge and queued in the write posting storage. In addition, the bus bridge includes a second mechanism for counting the number of write operations completed on the second bus. A mechanism for measuring the age of data held in each cache line of a coherent cache is also included as part of the bus bridge. Finally, the bus bridge includes a mechanism for delaying the completion of a read operation from the cache until all writes that were accepted by the bus bridge on the first bus before the cache data was fetched have been completed on the second bus. This is determined by comparing the age of the data held in a cache line to be read with the difference between the number of write operations received by the bus bridge and the number of write operations that have completed on the second bus.
摘要翻译：公开了一种总线桥，其提供两个计算机总线之间的接口，并且确保从一个总线相对于从另一个总线掌握的读取操作掌握的写入操作的正确排序，其中在总线桥中存在写入过帐存储可能导致排序违规。总线桥包括第一机制，用于对由总线桥接收并在写过帐存储中排队的写入操作的数量进行计数。此外，总线桥包括用于对在第二总线上完成的写入操作的数量进行计数的第二机制。用于测量保持在相干高速缓存的每个高速缓存行中的数据的年龄的机制也被包括在总线桥的一部分中。最后，总线桥包括用于延迟从高速缓存读取操作的完成的机制，直到在第二总线上已经完成在缓存数据被取出之前由第一总线上的总线桥接受的所有写入。这通过将要读取的高速缓存行中保存的数据的年龄与总线桥接收到的写入操作的数量与在第二总线上完成的写入操作的数量之间的差进行比较来确定。

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