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1. 发明授权

US06279081B1 System and method for performing memory fetches for an ATM card 有权
标题翻译：用于执行ATM卡的存储器提取的系统和方法
公开(公告)号：US06279081B1
公开(公告)日：2001-08-21
申请号：US09218226
申请日：1998-12-22
申请人： Thomas V Spencer , Robert J Horning , Monish S Shah
发明人： Thomas V Spencer , Robert J Horning , Monish S Shah
IPC分类号： G06F1200
CPC分类号： G06F12/0862
摘要： The present invention is generally directed to a system and method for fetching data from a system memory to an ATM card. The method includes the steps of receiving a request (via a PCI bus) to fetch data from memory, and identifying the request as an ATM request. The method then determines, based on the start address, the number of cache lines that will be implicated by the fetch. Then, the method automatically fetches the appropriate number of cache lines into the cache, and then passes the data to the ATM card, via the PCI bus. In accordance with another aspect of the present invention, a system is provided for fetching data from memory for an ATM card. Broadly, the system includes a system memory for data storage and a cache memory for providing high-speed (retrieval) temporary storage of data, the cache memory being disposed in communication with the system memory via a high-speed system bus. The system further includes a PCI bus in communication with the cache memory via an input/output (I/O) bus. A first mechanism is configured to identify a fetch for data from memory to the PCI bus by an ATM card. A second mechanism is configured to determine the number of lines of the cache memory that will be implicated by the identified fetch. Finally, a third mechanism is configured to automatically fetch the appropriate number of lines from the cache memory and to pass the data to the PCI bus.
摘要翻译：本发明一般涉及一种从系统存储器向ATM卡取出数据的系统和方法。该方法包括以下步骤：通过PCI总线接收从存储器提取数据的请求，并将该请求识别为ATM请求。然后，该方法基于开始地址确定将由提取涉及的高速缓存行的数量。然后，该方法自动将适当数量的高速缓存行提取到高速缓存中，然后通过PCI总线将数据传递到ATM卡。根据本发明的另一方面，提供一种用于从ATM卡的存储器取出数据的系统。广泛地说，该系统包括用于数据存储的系统存储器和用于提供数据的高速（检索）临时存储的高速缓冲存储器，该高速缓冲存储器经由高速系统总线被布置为与系统存储器通信。该系统还包括经由输入/输出（I / O）总线与高速缓冲存储器通信的PCI总线。第一机制被配置为通过ATM卡识别从存储器到PCI总线的数据的提取。第二机制被配置为确定将被识别的提取涉及的高速缓冲存储器的行数。最后，第三种机制被配置为从高速缓冲存储器自动获取适当数量的行并将数据传递到PCI总线。

2. 发明授权

US07035981B1 Asynchronous input/output cache having reduced latency 失效
标题翻译：异步输入/输出缓存具有降低的延迟
公开(公告)号：US07035981B1
公开(公告)日：2006-04-25
申请号：US09218333
申请日：1998-12-22
申请人： Thomas V Spencer , Monish S Shah
发明人： Thomas V Spencer , Monish S Shah
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F12/0835 , G06F2212/303
摘要： The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus. In accordance with another aspect of the present invention, a method is provided for buffering or caching data in a shared relationship between a system data bus and an input/output (I/O) data bus, which includes the steps of providing a single data storage area in communication with both a system data bus and an I/O data bus, and providing a single address storage area configured to store system memory addresses corresponding to data contemporaneously stored in the data storage area. In accordance with the broad aspect of the invention, the method further replicates a portion of validation circuitry in both a system frequency domain and an I/O frequency domain. In this way, latency delays encountered when crossing a frequency domain boundary are encountered at times outside a critical path.
摘要翻译：本发明一般涉及包括异步输入/输出（I / O）数据高速缓存的设备。该设备包括与系统数据总线和I / O数据总线通信的单个数据存储区域。类似地，设备包括地址存储区域，其被配置为存储对应于同时存储在数据存储区域中的数据的系统地址。该设备还包括第一电路，其被配置为指示数据存储区域内的数据的有效性状态，用于从I / O数据总线立即访问。类似的第二电路也被包括并且被配置为指示数据存储区域内的数据的有效性状态，用于从系统数据总线的立即访问。根据本发明的另一方面，提供一种用于在系统数据总线和输入/输出（I / O）数据总线之间的共享关系中缓存或缓存数据的方法，其包括以下步骤：提供单个数据存储区域与系统数据总线和I / O数据总线通信，并且提供单个地址存储区域，其被配置为存储对应于同时存储在数据存储区域中的数据的系统存储器地址。根据本发明的广泛方面，该方法进一步复制了系统频域和I / O频域中的一部分验证电路。这样，跨越关键路径的时候会遇到跨越频域边界时遇到的延迟延迟。

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