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1. 发明授权

US4958302A Graphics frame buffer with pixel serializing group rotator 失效
标题翻译：具有像素序列化组旋转器的图形帧缓冲器
公开(公告)号：US4958302A
公开(公告)日：1990-09-18
申请号：US86744
申请日：1987-08-18
申请人： Robert W. Fredrickson , Monish S. Shah
发明人： Robert W. Fredrickson , Monish S. Shah
IPC分类号： G09G5/36 , G09G5/39 , G09G5/395
CPC分类号： G09G5/395 , G09G5/39 , G09G2360/121 , G09G2360/122 , G09G5/363
摘要： A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM's. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separated cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput. A group rotator and associated group-sized shift register per bit-plane cooperate during refresh to reorder and serialize the pixels of sixteen by one tiles.
摘要翻译：图形系统使用由帧缓冲存储器组织支持的可编程块大小和形状，其中（X，Y）像素地址映射到RAM地址和数据线分配组上的定期偏移置换。这允许每个组中的一个RAM与每个其他组中的一个RAM一致地与存储器周期一起访问，直到组的数量。在这样的存储循环期间，每个RAM可以接收不同的地址。瓦片是与发送到RAM的地址集合相关联的像素位置的集合。由于排列的规则性质，这些位置可以是由单个边界限定的区域，该边界可以是矩形且具有变化的尺寸和形状。将（X，Y）像素地址更改为组的RAM地址会更改图块的大小和形状。瓷砖被缓存。 RGB像素值的瓷砖缓存在RGB缓存中，而Z值则缓存在分离的高速缓存中。缓存允许局部性的原理将较短的位周期替换到高速缓存用于帧缓冲器的存储器周期，从而提高存储器吞吐量。每个位平面的组旋转器和相关联的组大小的移位寄存器在刷新期间协作以重新排序和序列化16个乘法器的像素。

2. 发明授权

US4961153A Graphics frame buffer with strip Z buffering and programmable Z buffer location 失效
标题翻译：带有Z缓冲区和可编程Z缓冲区的图形帧缓冲区
公开(公告)号：US4961153A
公开(公告)日：1990-10-02
申请号：US86350
申请日：1987-08-18
申请人： Robert W. Fredrickson , Andrew C. Goris
发明人： Robert W. Fredrickson , Andrew C. Goris
IPC分类号： G09G5/36 , G09G5/39
CPC分类号： G09G5/39 , G09G2360/121 , G09G2360/122 , G09G5/363
摘要： A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM's. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput. The Z buffer for hidden surface removal need not be a full size frame buffer, as a lesser portion of frame buffer is, if need be, used repeatedly. The location of such a lesser size Z buffer in the overall frame buffer is programmable.
摘要翻译：图形系统使用由帧缓冲存储器组织支持的可编程块大小和形状，其中（X，Y）像素地址映射到RAM地址和数据线分配组上的定期偏移置换。这允许每个组中的一个RAM与每个其他组中的一个RAM一致地与存储器周期一起访问，直到组的数量。在这样的存储循环期间，每个RAM可以接收不同的地址。瓦片是与发送到RAM的地址集合相关联的像素位置的集合。由于排列的规则性质，这些位置可以是由单个边界限定的区域，该边界可以是矩形且具有变化的尺寸和形状。将（X，Y）像素地址更改为组的RAM地址会更改图块的大小和形状。瓷砖被缓存。 RGB像素值的瓷砖缓存在RGB缓存中，而Z值缓存在单独的高速缓存中。缓存允许局部性的原理将较短的位周期替换到高速缓存用于帧缓冲器的存储器周期，从而提高存储器吞吐量。用于隐藏表面去除的Z缓冲区不需要是全尺寸帧缓冲区，因为如果需要，帧缓冲区的较小部分被重复使用。这种较小尺寸Z缓冲器在整个帧缓冲器中的位置是可编程的。

3. 发明授权

US5131080A Graphics frame buffer with RGB pixel cache 失效
标题翻译：具有RGB像素缓存的图形帧缓冲区
公开(公告)号：US5131080A
公开(公告)日：1992-07-14
申请号：US632582
申请日：1990-12-20
申请人： Robert W. Fredrickson , Andrew C. Goris
发明人： Robert W. Fredrickson , Andrew C. Goris
IPC分类号： G09G5/02 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/397
CPC分类号： G09G5/026 , G06F12/0875 , G09G5/06 , G09G5/363 , G09G5/397 , G09G2360/121 , G09G2360/122 , G09G2360/127
摘要： A graphics system uses a programmable tile size shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in each group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM's. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. Tiles are cached. Tiles for RGB pixel are cached in an RGB cache, while Z values are cached in a separate cache. Caching allows the principle of locality to substitute shorter bit-cycles to the cache for memory cycles to the frame buffer, resulting in improved memory throughput.
摘要翻译：图形系统使用由帧缓冲存储器组织支持的可编程块大小形状，其中（X，Y）像素地址映射到RAM地址和数据线分配组上的定期偏移置换。这允许每个组中的一个RAM与每个其他组中的一个RAM一致地与存储器周期一起访问，直到组的数量。在这样的存储循环期间，每个RAM可以接收不同的地址。瓦片是与发送到RAM的地址集合相关联的像素位置的集合。由于排列的规则性质，这些位置可以是由单个边界限定的区域，该边界可以是矩形且具有变化的尺寸和形状。将（X，Y）像素地址更改为组的RAM地址会更改图块的大小和形状。瓷砖被缓存。 RGB像素的瓷砖缓存在RGB缓存中，而Z值则缓存在单独的高速缓存中。缓存允许局部性的原理将较短的位周期替换到高速缓存用于帧缓冲器的存储器周期，从而提高存储器吞吐量。

4. 发明授权

US4367465A Graphics light pen and method for raster scan CRT 失效
标题翻译：图形光笔和光栅扫描方法
公开(公告)号：US4367465A
公开(公告)日：1983-01-04
申请号：US137103
申请日：1980-04-04
申请人： Nicholas P. Mati , Frederick J. Porter , Robert W. Fredrickson
发明人： Nicholas P. Mati , Frederick J. Porter , Robert W. Fredrickson
IPC分类号： G06F3/023 , G06F3/033 , G06F3/037 , G06F3/038 , G06F3/048 , G06F3/153 , G09G1/16
CPC分类号： G06F3/037 , G06F3/0383 , G06F3/04892
摘要： A graphics system for a raster scan CRT implements a light pen tracked by a cursor. Hits corresponding to the cursor are distinguished from those corresponding to background data by a selective interlacing technique. A threshold level shifting technique providing accurate measurement of a horizontal component of the cursor allows accurate prediction of the location of the center of the field of view during the next frame.
摘要翻译：用于光栅扫描CRT的图形系统实现由光标跟踪的光笔。通过选择性隔行扫描技术将对应于游标的命中与对应于背景数据的命中区分开。提供对光标的水平分量的精确测量的阈值电平移位技术允许在下一帧期间精确地预测视场中心的位置。

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