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1. 发明申请

US20110119475A1 GLOBAL SYNCHRONIZATION OF PARALLEL PROCESSORS USING CLOCK PULSE WIDTH MODULATION 有权
标题翻译：使用时钟脉冲宽度调制的并行处理器的全局同步
公开(公告)号：US20110119475A1
公开(公告)日：2011-05-19
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/12 , G06F1/10 , G06F9/00 , G06F1/08
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

2. 发明申请

US20100231281A1 SELF-TEST DESIGN METHODOLOGY AND TECHNIQUE FOR ROOT-GATED CLOCKING STRUCTURE 有权
标题翻译：自闭式钟表结构的自我测试设计方法与技术
公开(公告)号：US20100231281A1
公开(公告)日：2010-09-16
申请号：US12401730
申请日：2009-03-11
申请人： Steven M. Douskey , Ryan A. Fitch , Brandon E. Schenck
发明人： Steven M. Douskey , Ryan A. Fitch , Brandon E. Schenck
IPC分类号： H03K3/00
CPC分类号： G01R31/31727 , G06F1/04 , G06F1/10
摘要： In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.
摘要翻译：在产生用于电平敏感扫描设计锁存器的时钟信号的方法中，至少一个测试输入信号被发送到多个分离器叶片。一旦测试输入信号稳定在每个分路器叶片，则产生具有来自中央根部的预定脉冲模式的整形振荡器时钟信号。在多个分路器叶片处，测试输入信号与整形振荡器时钟信号逻辑组合，从而产生第一锁存时钟信号和第二锁存时钟信号。逻辑组合动作包括将小于一个时钟周期的延迟施加到整形振荡器时钟信号以产生延迟的振荡器时钟信号; 将延迟的振荡器时钟信号与第二信号逻辑地组合，以便产生第一锁存时钟信号; 并且将所述整形振荡器时钟信号与第三信号逻辑地组合，以便产生所述第二锁存时钟信号。

3. 发明授权

US08412974B2 Global synchronization of parallel processors using clock pulse width modulation 有权
标题翻译：使用时钟脉宽调制的并行处理器的全局同步
公开(公告)号：US08412974B2
公开(公告)日：2013-04-02
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

4. 发明授权

US07830195B2 Self-test design methodology and technique for root-gated clocking structure 有权
标题翻译：根门式时钟结构的自检设计方法和技术
公开(公告)号：US07830195B2
公开(公告)日：2010-11-09
申请号：US12401730
申请日：2009-03-11
申请人： Steven M. Douskey , Ryan A. Fitch , Brandon E. Schenck
发明人： Steven M. Douskey , Ryan A. Fitch , Brandon E. Schenck
IPC分类号： G06F1/04
CPC分类号： G01R31/31727 , G06F1/04 , G06F1/10
摘要： In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.
摘要翻译：在产生用于电平敏感扫描设计锁存器的时钟信号的方法中，至少一个测试输入信号被发送到多个分离器叶片。一旦测试输入信号稳定在每个分路器叶片，则产生具有来自中央根部的预定脉冲模式的整形振荡器时钟信号。在多个分路器叶片处，测试输入信号与整形振荡器时钟信号逻辑组合，从而产生第一锁存时钟信号和第二锁存时钟信号。逻辑组合动作包括将小于一个时钟周期的延迟施加到整形振荡器时钟信号以产生延迟的振荡器时钟信号; 将延迟的振荡器时钟信号与第二信号逻辑地组合，以便产生第一锁存时钟信号; 并且将所述整形振荡器时钟信号与第三信号逻辑地组合，以便产生所述第二锁存时钟信号。

5. 发明申请

US20090150103A1 Computer-Based Method and System for Simulating Static Timing Clocking Results 审中-公开
标题翻译：基于计算机的方法和系统，用于模拟静态时序时钟结果
公开(公告)号：US20090150103A1
公开(公告)日：2009-06-11
申请号：US11951593
申请日：2007-12-06
申请人： Matthew Roger Ellavsky , Brandon E. Schenck , Jing Zhang
发明人： Matthew Roger Ellavsky , Brandon E. Schenck , Jing Zhang
IPC分类号： G01R29/02
CPC分类号： G01R31/31727 , G01R31/318357
摘要： A method, system and computer-readable medium are presented for creating unique clock waveform checking commands for an event simulator to validate that the logical creation matches the timing definitions. The method includes selecting one or more clock signals for validation; specifying timing definitions of the selected clock signals; automatically categorizing the selected clock signals based on their synchrony; automatically matching each selected clock signal to a corresponding clock cycle by parsing the specified timing definitions; specifying one or more test cases for an event simulator, wherein the test cases simulate logic for generating each selected clock signal; validating that the logic for generating each selected clock signal matches the specified timing definitions for each selected clock signal.
摘要翻译：提出了一种方法，系统和计算机可读介质，用于为事件模拟器创建独特的时钟波形检查命令，以验证逻辑创建与定时定义相匹配。该方法包括选择一个或多个时钟信号进行验证; 指定所选择的时钟信号的定时定义; 根据其同步自动对所选择的时钟信号进行分类; 通过解析指定的定时定义，将每个选定的时钟信号自动匹配到相应的时钟周期; 为事件模拟器指定一个或多个测试用例，其中所述测试用例模拟用于产生每个所选时钟信号的逻辑; 验证用于产生每个选定时钟信号的逻辑与每个所选择的时钟信号的指定定时定义相匹配。

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