专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120290995A1 CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST 失效
标题翻译：更改缓存器在网络列表中的位置
公开(公告)号：US20120290995A1
公开(公告)日：2012-11-15
申请号：US13106005
申请日：2011-05-12
申请人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
发明人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/505 , G06F17/5068
摘要： In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.
摘要翻译：在一个实施例中，缓冲器托架由可移动对象表示，该可移动对象在网表中具有单位内的位置。表示缓冲区的可移动对象的位置将更改为网络列表中的新位置，如果更改位置可改善单元中的位置。在一个实施例中，在确定是否将位置改变到新位置时，考虑将可移动物体连接到人造针的网的净重。在一个实施例中，在确定是否将位置改变到新位置时考虑包围该位置的边界区域。

2. 发明授权

US06990645B2 Method for static timing verification of integrated circuits having voltage islands 失效
标题翻译：具有电压岛的集成电路的静态定时验证方法
公开(公告)号：US06990645B2
公开(公告)日：2006-01-24
申请号：US10249661
申请日：2003-04-29
申请人： Susan K. Lichtensteiger , Phillip P. Normand , Timothy M. Platt
发明人： Susan K. Lichtensteiger , Phillip P. Normand , Timothy M. Platt
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analysis of an integrated circuit design having multiple voltage islands, including: (a) determining a clock path through the voltage islands; (b) determining a data path through the voltage islands; (c) determining which voltage islands are independent voltage islands; (d) determining which voltage islands are dependent voltage islands; (e) for the data path and the clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths; and (f) for the data path and the clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths.
摘要翻译：一种具有多个电压岛的集成电路设计的分析方法，包括：（a）确定通过电压岛的时钟路径; （b）确定通过电压岛的数据路径; （c）确定哪些电压岛是独立的电压岛; （d）确定哪些电压岛是相关电压岛; （e）对于数据路径和时钟路径，基于数据和时钟路径中每个独立和相关电压岛的最小和最大工作电压执行最差情况的静态时序分析; 和（f）对于数据路径和时钟路径，基于数据和时钟路径中每个独立和相关电压岛的最小和最大工作电压执行最佳情况的静态时序分析。

3. 发明授权

US08413104B2 Changing the location of a buffer bay in a netlist 失效
标题翻译：更改网表中缓冲区的位置
公开(公告)号：US08413104B2
公开(公告)日：2013-04-02
申请号：US13106005
申请日：2011-05-12
申请人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
发明人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072 , G06F17/505 , G06F17/5068
摘要： In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.
摘要翻译：在一个实施例中，缓冲器托架由可移动对象表示，该可移动对象在网表中具有单位内的位置。表示缓冲区的可移动对象的位置将更改为网络列表中的新位置，如果更改位置可改善单元中的位置。在一个实施例中，在确定是否将位置改变到新位置时，考虑将可移动物体连接到人造针的网的净重。在一个实施例中，在确定是否将位置改变到新位置时考虑包围该位置的边界区域。

4. 发明授权

US08448121B2 Implementing Z directional macro port assignment 失效
标题翻译：实现Z方向宏端口分配
公开(公告)号：US08448121B2
公开(公告)日：2013-05-21
申请号：US13208046
申请日：2011-08-11
申请人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
发明人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/66
摘要： A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现用于异构分层集成电路芯片的随机逻辑宏的增强的Z方向宏端口分配或三维端口创建。在宏的层上提供初始端口布局。初始端口放置被扩展以提供包括沿z轴的多个金属层的三维端口形状。在扩展的三维端口形状内定义每个宏级和芯片顶级的布线。扩大的三维端口形状的每个不必要的金属层被去除，提供最终的三维端口形状。

5. 发明申请

US20120110533A1 IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES 有权
标题翻译：实施增强时钟树分布到N层次分层实体
公开(公告)号：US20120110533A1
公开(公告)日：2012-05-03
申请号：US12914573
申请日：2010-10-28
申请人： Mark R. Lasher , Daniel R. Menard , Phillip P. Normand
发明人： Mark R. Lasher , Daniel R. Menard , Phillip P. Normand
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5072 , G06F17/5081 , G06F2217/62
摘要： A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.
摘要翻译：一种用于实现增强时钟树分布以在集成电路芯片的N级分层实体上去耦的方法，系统和计算机程序产品。构建本地时钟树分布。构建顶级时钟树分布。然后提供构建和路由一个顶级时钟树。本地时钟树分布和顶层时钟树分布是独立构建的，每个时钟树分布都使用高性能缓冲区的等效本地时钟分配来平衡时钟块区域。

6. 发明申请

US20130042214A1 IIMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT 失效
标题翻译：取消Z方向广域网端口分配
公开(公告)号：US20130042214A1
公开(公告)日：2013-02-14
申请号：US13208046
申请日：2011-08-11
申请人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
发明人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
IPC分类号： G06F9/45
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/66
摘要： A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现用于异构分层集成电路芯片的随机逻辑宏的增强的Z方向宏端口分配或三维端口创建。在宏的层上提供初始端口布局。初始端口放置被扩展以提供包括沿z轴的多个金属层的三维端口形状。在扩展的三维端口形状内定义每个宏级和芯片顶级的布线。扩大的三维端口形状的每个不必要的金属层被去除，提供最终的三维端口形状。

7. 发明授权

US08356264B2 Implementing enhanced clock tree distributions to decouple across N-level hierarchical entities 有权
标题翻译：实现增强的时钟树分布，以跨越N级分层实体去耦合
公开(公告)号：US08356264B2
公开(公告)日：2013-01-15
申请号：US12914573
申请日：2010-10-28
申请人： Mark R. Lasher , Daniel R. Menard , Phillip P. Normand
发明人： Mark R. Lasher , Daniel R. Menard , Phillip P. Normand
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5072 , G06F17/5081 , G06F2217/62
摘要： A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.
摘要翻译：一种用于实现增强时钟树分布以在集成电路芯片的N级分层实体上去耦的方法，系统和计算机程序产品。构建本地时钟树分布。构建顶级时钟树分布。然后提供构建和路由一个顶级时钟树。本地时钟树分布和顶层时钟树分布是独立构建的，每个时钟树分布都使用高性能缓冲区的等效本地时钟分配来平衡时钟块区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式