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1. 发明申请

US20140015504A1 VOLTAGE GENERATING CIRCUIT 有权
标题翻译：电压发生电路
公开(公告)号：US20140015504A1
公开(公告)日：2014-01-16
申请号：US14009715
申请日：2012-04-09
申请人： Shinya Sano , Masashi Horiguchi , Takahiro Miki , Mitsuru Hiraki
发明人： Shinya Sano , Masashi Horiguchi , Takahiro Miki , Mitsuru Hiraki
IPC分类号： H02M3/158
CPC分类号： G05F3/267 , G05F3/20 , G05F3/26 , G05F3/30 , H02M3/158
摘要： A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
摘要翻译：其中放大器的偏移对输出电压的影响减小的电压产生电路具有在相同电位的发射极端子的第一和第二双极晶体管（Q1，Q2）。 Q1的基极端子设置在Q2的集电极侧。第一电阻元件将Q2的集电极侧与Q2的基极侧连接; 并且第二电阻元件（R1）将Q1的集电极侧连接到R2。第三电阻元件（R3）将Q2的基极端子与发射极端子的电位相连。放大器（A1）输出基于Q1和Q2的集电极侧之间的电压差的电压; 电压电流转换部（MP1，MP2）将放大器输出转换为R1和R2的连接节点的电流。然后基于所产生的电流输出电压。

2. 发明授权

US08073643B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08073643B2
公开(公告)日：2011-12-06
申请号：US12122715
申请日：2008-05-18
申请人： Takayasu Ito , Mitsuru Hiraki , Masashi Horiguchi , Toyohiro Shimogawa
发明人： Takayasu Ito , Mitsuru Hiraki , Masashi Horiguchi , Toyohiro Shimogawa
IPC分类号： G01R21/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A semiconductor device which includes a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down, and an internal voltage determining circuit for determining the voltage of the internal power supply in which power is shut down. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When the power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, the increased voltage of the internal power supply is determined by the internal voltage determining circuit, operation of a circuit block is started, and the switch is turned on.
摘要翻译：一种半导体装置，包括连接未关闭电源的内部电源的电源开关和关闭电力的内部电源;以及内部电压确定电路，其用于确定内部电源的电压，其中，被关闭当内部电源的电源中断时，电源开关关闭，调节器电路关闭，调节器电路的输出短路到地电位。当恢复内部电源的电源时，调节器电路接通，短路被取消，内部电源的增加的电压由内部电压确定电路确定，电路块的操作开始，开关打开

3. 发明授权

US07821862B2 Semiconductor memory circuit 有权
标题翻译：半导体存储电路
公开(公告)号：US07821862B2
公开(公告)日：2010-10-26
申请号：US11902877
申请日：2007-09-26
申请人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
发明人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译：本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。

4. 发明授权

US07693000B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07693000B2
公开(公告)日：2010-04-06
申请号：US12252241
申请日：2008-10-15
申请人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
发明人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
IPC分类号： G11C8/00
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
摘要翻译：在具有能够向每个存储单元输入写入数据的数据输入缓冲器的半导体器件中，在接收到对存储器单元进行的写入操作的指令之后，数据输入缓冲器从非活动状态改变为有效状态。数据输入缓冲器是具有基于SSTL的接口规范的差分输入缓冲器; 通过电源开关的导通而使其成为活动状态，从而在紧接着小振幅信号的小变化之后立即进行通过电流的流动并接收信号。由于只有在提供了写入操作对存储器单元的指令的情况下，输入缓冲器才进入活动状态，所以在提供写入操作的指令之前，预先使数据输入缓冲器无效，从而减少浪费的功耗。在另一方面，通过在从写入命令发布到下一个命令发布的时间段内从主动状态变为非活动状态来降低功耗。

5. 发明申请

US20080297220A1 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
公开(公告)号：US20080297220A1
公开(公告)日：2008-12-04
申请号：US12153385
申请日：2008-05-19
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H03K3/356
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

6. 发明授权

US07138722B2 Semiconductor device 有权
公开(公告)号：US07138722B2
公开(公告)日：2006-11-21
申请号：US11057495
申请日：2005-02-15
申请人： Toshio Miyamoto , Asao Nishimura , Koki Noguchi , Satoshi Michishita , Masashi Horiguchi , Masaharu Kubo , Kazuyoshi Shiba
发明人： Toshio Miyamoto , Asao Nishimura , Koki Noguchi , Satoshi Michishita , Masashi Horiguchi , Masaharu Kubo , Kazuyoshi Shiba
IPC分类号： H01L23/48
CPC分类号： H01L24/50 , H01L23/49572 , H01L23/49816 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L27/10897 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/16245 , H01L2224/451 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2225/1029 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01055 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12033 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2924/3511 , H01L2924/00015 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

7. 发明申请

US20060239103A1 Semiconductor memory circuit 有权
公开(公告)号：US20060239103A1
公开(公告)日：2006-10-26
申请号：US11472252
申请日：2006-06-22
申请人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
发明人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

8. 发明授权

US07106643B2 Method for manufacturing memory device provided with a defect recovery mechanism featuring a redundancy circuit 失效
标题翻译：一种具有冗余电路的缺陷恢复机构的存储装置的制造方法
公开(公告)号：US07106643B2
公开(公告)日：2006-09-12
申请号：US11139513
申请日：2005-05-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C29/04 , G11C29/18 , G11C29/24 , G11C8/12
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：用于制造存储器件的方法，所述存储器是具有备用位线的存储器阵列，并且提供具有冗余电路的缺陷恢复方案。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

9. 发明申请

US20060120125A1 Semiconductor memory device and defect remedying method thereof 失效
公开(公告)号：US20060120125A1
公开(公告)日：2006-06-08
申请号：US11330220
申请日：2006-01-12
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C19/08
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

10. 发明授权

US07023237B2 Semiconductor integrated circuits with power reduction mechanism 失效
公开(公告)号：US07023237B2
公开(公告)日：2006-04-04
申请号：US11004823
申请日：2004-12-07
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K17/16
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

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