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1. 发明申请

US20080297220A1 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
公开(公告)号：US20080297220A1
公开(公告)日：2008-12-04
申请号：US12153385
申请日：2008-05-19
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H03K3/356
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

2. 发明授权

US06307236B1 Semiconductor integrated circuit device 有权
公开(公告)号：US06307236B1
公开(公告)日：2001-10-23
申请号：US09155801
申请日：1998-10-06
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L2972
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.

3. 发明授权

US07781814B2 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
标题翻译：形成具有不同厚度的栅极绝缘膜的CMOS结构的方法
公开(公告)号：US07781814B2
公开(公告)日：2010-08-24
申请号：US12153385
申请日：2008-05-19
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L29/72
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
摘要翻译：半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。

4. 发明授权

US07427791B2 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
标题翻译：形成具有不同厚度的栅极绝缘膜的CMOS结构的方法
公开(公告)号：US07427791B2
公开(公告)日：2008-09-23
申请号：US11118951
申请日：2005-05-02
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L29/72
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
摘要翻译：半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。

5. 发明授权

US08674419B2 Method of forming a CMOS structure having gate insulation films of different thicknesses 失效
标题翻译：形成具有不同厚度的栅极绝缘膜的CMOS结构的方法
公开(公告)号：US08674419B2
公开(公告)日：2014-03-18
申请号：US12838598
申请日：2010-07-19
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L29/72
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
摘要翻译：半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。

6. 发明申请

US20110012180A1 METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES 失效
标题翻译：形成具有不同厚度的门绝缘膜的CMOS结构的方法
公开(公告)号：US20110012180A1
公开(公告)日：2011-01-20
申请号：US12838598
申请日：2010-07-19
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L29/72 , H01L27/088
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
摘要翻译：半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。

7. 发明申请

US20050190608A1 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
标题翻译：形成具有不同厚度的栅极绝缘膜的CMOS结构的方法
公开(公告)号：US20050190608A1
公开(公告)日：2005-09-01
申请号：US11118951
申请日：2005-05-02
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L21/8234 , H01L27/088 , G11C11/34
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The present invention is drawn to a semiconductor integrated circuit device employing employs on the same silicon substrate a plurality of kinds of MOS transistors with different in magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.
摘要翻译：本发明涉及一种半导体集成电路器件，其采用在同一硅衬底上采用在源极和栅极之间或其漏极和栅极之间流动的隧道电流大小不同的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。控制电路响应于接收到提供给其的控制信号，以控制在主电路使用的隧道电流增加的MOS晶体管的源极和栅极之间或漏极和栅极之间的电流的流动，在一段时间内选择性地允许电流，并且在另一时段期间被禁止。

8. 发明授权

US06500715B2 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
标题翻译：形成具有不同厚度的栅极绝缘膜的CMOS结构的方法
公开(公告)号：US06500715B2
公开(公告)日：2002-12-31
申请号：US09852793
申请日：2001-05-11
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L218234
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.
摘要翻译：本发明涉及一种半导体集成电路器件，该半导体集成电路器件在相同的硅衬底上采用在源极和栅极之间或其漏极和栅极之间流动的隧道电流大小不同的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减小或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。控制电路响应于接收到提供给其的控制信号，以控制在主电路使用的隧道电流增加的MOS晶体管的源极和栅极之间或漏极和栅极之间的电流的流动，以这种方式在一段时间内选择性地允许电流，并且在另一个时间段内禁止电流。

9. 发明申请

US20140015504A1 VOLTAGE GENERATING CIRCUIT 有权
标题翻译：电压发生电路
公开(公告)号：US20140015504A1
公开(公告)日：2014-01-16
申请号：US14009715
申请日：2012-04-09
申请人： Shinya Sano , Masashi Horiguchi , Takahiro Miki , Mitsuru Hiraki
发明人： Shinya Sano , Masashi Horiguchi , Takahiro Miki , Mitsuru Hiraki
IPC分类号： H02M3/158
CPC分类号： G05F3/267 , G05F3/20 , G05F3/26 , G05F3/30 , H02M3/158
摘要： A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
摘要翻译：其中放大器的偏移对输出电压的影响减小的电压产生电路具有在相同电位的发射极端子的第一和第二双极晶体管（Q1，Q2）。 Q1的基极端子设置在Q2的集电极侧。第一电阻元件将Q2的集电极侧与Q2的基极侧连接; 并且第二电阻元件（R1）将Q1的集电极侧连接到R2。第三电阻元件（R3）将Q2的基极端子与发射极端子的电位相连。放大器（A1）输出基于Q1和Q2的集电极侧之间的电压差的电压; 电压电流转换部（MP1，MP2）将放大器输出转换为R1和R2的连接节点的电流。然后基于所产生的电流输出电压。

10. 发明授权

US08073643B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08073643B2
公开(公告)日：2011-12-06
申请号：US12122715
申请日：2008-05-18
申请人： Takayasu Ito , Mitsuru Hiraki , Masashi Horiguchi , Toyohiro Shimogawa
发明人： Takayasu Ito , Mitsuru Hiraki , Masashi Horiguchi , Toyohiro Shimogawa
IPC分类号： G01R21/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A semiconductor device which includes a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down, and an internal voltage determining circuit for determining the voltage of the internal power supply in which power is shut down. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When the power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, the increased voltage of the internal power supply is determined by the internal voltage determining circuit, operation of a circuit block is started, and the switch is turned on.
摘要翻译：一种半导体装置，包括连接未关闭电源的内部电源的电源开关和关闭电力的内部电源;以及内部电压确定电路，其用于确定内部电源的电压，其中，被关闭当内部电源的电源中断时，电源开关关闭，调节器电路关闭，调节器电路的输出短路到地电位。当恢复内部电源的电源时，调节器电路接通，短路被取消，内部电源的增加的电压由内部电压确定电路确定，电路块的操作开始，开关打开

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