专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06449669B1 Method and apparatus for providing bimodal voltage references for differential signaling 失效
标题翻译：用于提供差分信号的双峰电压参考的方法和装置
公开(公告)号：US06449669B1
公开(公告)日：2002-09-10
申请号：US09385977
申请日：1999-08-30
申请人： Eric J. Dahlen , Leonard W. Cross
发明人： Eric J. Dahlen , Leonard W. Cross
IPC分类号： G06F1314
CPC分类号： G06F1/26
摘要： According to the invention, systems, apparatus and methods are disclosed for providing bimodal voltage references for use in differential signaling between components or devices. In an embodiment, a switchable power supply is used to produce at least one of two or more supply voltages based on the value of a selection signal received by the switchable power supply. This selection signal is also used by at least one of the elements to switch between a reference voltage produced by another device and a reference voltage derived from the supply voltage. In certain embodiments, the reference voltage derived from the power supply and the selection via a multiplexing circuit is contained within one of the devices (e.g., a chip), which provides certain design and cost advantages.
摘要翻译：根据本发明，公开了用于提供用于组件或设备之间的差分信令的双峰电压参考的系统，装置和方法。在一个实施例中，可切换电源用于基于由可切换电源接收的选择信号的值来产生两个或更多个电源电压中的至少一个。该选择信号还被至少一个元件用于在另一器件产生的参考电压与从电源电压导出的参考电压之间切换。在某些实施例中，从电源得到的参考电压和通过复用电路的选择被包含在提供某种设计和成本优点的设备（例如，芯片）之一内。

2. 发明授权

US6085325A Method and apparatus for supporting power conservation operation modes 失效
标题翻译：支持节电运行模式的方法和装置
公开(公告)号：US6085325A
公开(公告)日：2000-07-04
申请号：US766089
申请日：1996-12-16
申请人： David R. Jackson , Leonard W. Cross , Robert A. Jacobs , Ali S. Oztaskin
发明人： David R. Jackson , Leonard W. Cross , Robert A. Jacobs , Ali S. Oztaskin
IPC分类号： G06F1/04 , G06F1/08 , G06F1/32 , G06F13/38 , G06F1/26 , G06F1/28
CPC分类号： G06F1/3237 , G06F1/08 , G06F1/32 , G06F1/325 , Y02B60/1221
摘要： An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.
摘要翻译：描述了一种用于管理从总线接收电力的电子装置中的电力的装置。该装置包括时钟使能电路，其禁止产生从接收第一信号时由振荡器输出的原始频率导出的标称时钟频率的时钟。时间独立的时间参考电路耦合到时钟使能电路。时间独立的时间参考电路在接收到进入暂停状态的信号之后的第一预定时间段内将第一信号发送到时钟使能电路。

3. 发明授权

US5602878A Method of delivering stable data across an asynchronous interface 失效
标题翻译：通过异步接口传递稳定数据的方法
公开(公告)号：US5602878A
公开(公告)日：1997-02-11
申请号：US311679
申请日：1994-09-23
申请人： Leonard W. Cross
发明人： Leonard W. Cross
IPC分类号： H04L7/02 , H04L7/00
CPC分类号： H04L7/02 , H04L7/0041
摘要： The present invention relates to a method and apparatus for asynchronously transferring data from a first synchronous sequential logic circuit which derives its clock source from a first clock to a second synchronous sequential logic circuit which derives its clock source from a second clock, whereby metastability of the second synchronous sequential logic circuit is avoided. The invention comprises a data path and a control path; a data synchronizer coupled to the data path for synchronizing data signals; a control synchronizer coupled to the control path for synchronizing control signals; a register coupled in parallel to the data path for storing valid data output from the data synchronizer; a multiplexor having one input coupled to the data path, another input coupled to the register, a selector input coupled to the control path for selecting between receiving as input synchronized data signals or the contents of the register, and an output for transmitting valid data. If metastability is unlikely, the control signal is deasserted causing the multiplexor to select the synchronized data as input. If metastability is likely, the synchronized control signal is asserted causing the multiplexor to select the register as input. The basic test is whether to accept the new state of the data signal or wait and use the old state currently maintained in the register, until such time as the likelihood of metastability has passed, as indicated by the synchronized control signal.
摘要翻译：本发明涉及一种用于从第一同步顺序逻辑电路异步传送数据的方法和装置，其将其时钟源从第一时钟导出到第二同步顺序逻辑电路，该第二同步顺序逻辑电路从第二时钟导出其时钟源，避免了第二同步顺序逻辑电路。本发明包括数据路径和控制路径; 数据同步器，耦合到数据路径，用于同步数据信号; 耦合到控制路径的控制同步器，用于使控制信号同步; 与数据路径并行耦合的寄存器，用于存储从数据同步器输出的有效数据; 多路复用器，其具有耦合到数据路径的一个输入端，耦合到该寄存器的另一输入端，耦合到该控制路径的选择器输入端，用于在接收作为输入同步数据信号或寄存器的内容之间进行选择，以及用于发送有效数据的输出。如果亚稳态不太可能，则控制信号被解除无效，导致多路复用器选择同步数据作为输入。如果亚稳态可能，则同步控制信号被断言，导致多路复用器选择该寄存器作为输入。基本测试是接受数据信号的新状态还是等待并使用当前维护在寄存器中的旧状态，直到达到亚稳态的可能性为止，如同步控制信号所示。

4. 发明授权

US5353431A Memory address decoder with storage for memory attribute information 失效
标题翻译：内存地址解码器，用于存储内存属性信息
公开(公告)号：US5353431A
公开(公告)日：1994-10-04
申请号：US193516
申请日：1994-02-08
申请人： Patrick F. Doyle , Leonard W. Cross , Roger Noar
发明人： Patrick F. Doyle , Leonard W. Cross , Roger Noar
IPC分类号： G06F12/06 , G06F12/02
CPC分类号： G06F12/0684
摘要： A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The memory address decoder includes an SRAM for storing a memory map which associates memory attributes with memory ranges or blocks of memory. The memory attributes include: memory residence, caching, write protection of memory ranges, and the decoding of other memory modules. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode. A default power up mode is entered after power is first applied to the computer system. When the processor specifies a programming mode, the processor may write data directly into the SRAM. When the processor specifies the read back mode, the contents of the SRAM may be read back by the processor through the read back register. A normal mode may be entered in order to enable access to system memory (DRAM) with memory attribute information.
摘要翻译：用于计算机系统的可编程和可测试的存储器地址解码器，其中静态随机存取存储器件用于存储存储器配置信息。计算机系统包括经由数据和地址线耦合到存储器地址解码器的处理器。存储器地址解码器包括用于存储将存储器属性与存储器范围或存储器块相关联的存储器映射的SRAM。内存属性包括：内存驻留，缓存，内存范围的写保护以及其他内存模块的解码。本发明还包括控制逻辑，回读寄存器和用于控制SRAM的加载和回读验证的模式寄存器。控制逻辑以四种模式之一操作存储器地址解码器。这些模式包括：1）上电模式，2）编程模式，3）回读模式，4）正常运行模式。通过将模式寄存器加载到与所需模式相对应的值来选择这些模式之一。电源首次应用于计算机系统后，将输入默认上电模式。当处理器指定编程模式时，处理器可以将数据直接写入SRAM。当处理器指定回读模式时，SRAM的内容可以由处理器通过读回寄存器读回。可以输入正常模式以便能够访问具有存储器属性信息的系统存储器（DRAM）。

5. 发明授权

US06769041B2 Method and apparatus for providing bimodal voltage references for differential signaling 失效
标题翻译：用于提供差分信号的双峰电压参考的方法和装置
公开(公告)号：US06769041B2
公开(公告)日：2004-07-27
申请号：US10114157
申请日：2002-04-01
申请人： Eric J. Dahlen , Leonard W. Cross
发明人： Eric J. Dahlen , Leonard W. Cross
IPC分类号： G06F1314
CPC分类号： G06F1/26
摘要： According to an embodiment of the invention, systems, apparatus and methods are disclosed for providing bimodal voltage references for use in differential signaling between components or devices. According to an embodiment, a switchable power supply is used to produce at least one of two or more supply voltages based on the value of a selection signal received by the switchable power supply. This selection signal is also used by at least one of the elements to switch between a reference voltage produced by another device and a reference voltage derived from the supply voltage. In certain embodiments, the reference voltage derived from the power supply and the selection via a multiplexing circuit is contained within one of the devices (e.g., a chip), which provides certain design and cost advantages.
摘要翻译：根据本发明的实施例，公开了用于提供用于组件或设备之间的差分信令中的双峰电压参考的系统，装置和方法。根据实施例，可切换电源用于基于由可切换电源接收的选择信号的值来产生两个或更多个电源电压中的至少一个。该选择信号还被至少一个元件用于在另一器件产生的参考电压与从电源电压导出的参考电压之间切换。在某些实施例中，从电源得到的参考电压和通过复用电路的选择被包含在提供某种设计和成本优点的设备（例如，芯片）之一内。

6. 发明授权

US5982425A Method and apparatus for draining video data from a planarized video buffer 失效
标题翻译：从平面化视频缓冲器中排出视频数据的方法和装置
公开(公告)号：US5982425A
公开(公告)日：1999-11-09
申请号：US772701
申请日：1996-12-23
申请人： John Lewis Allen , Leonard W. Cross , Bill A. Munson , Ali S. Oztaskin , Roger Traylor
发明人： John Lewis Allen , Leonard W. Cross , Bill A. Munson , Ali S. Oztaskin , Roger Traylor
IPC分类号： H04N9/64 , H04N5/76 , H04N3/14
CPC分类号： H04N9/64
摘要： A method and apparatus for draining video data from a planarized video buffer in a video camera. The method includes the steps of reading a first sequence of video data from a first plane of the planarized image buffer starting at a buffer address indicated by a first pointer, and then reading a second sequence of video data from a second plane of the planarized image buffer starting at a buffer address indicated by a second read pointer. The apparatus includes an address generation unit and a sequence counter. The address generation unit includes a number of read pointers each configured to indicate a memory location within a different data plane of a video buffer. The address unit is configured to address a sequence of memory locations in a video buffer starting at a location indicated by an active one of the read pointers. The sequence counter is configured to detect when a final memory location of the sequence of memory locations has been addressed by the address generation unit and, in response, to select a different one of the read pointers to be the active read pointer.
摘要翻译：一种用于从视频摄像机中的平面化视频缓冲器排出视频数据的方法和装置。该方法包括从平坦化图像缓冲器的第一平面读取第一序列的视频数据的步骤，从由第一指针指示的缓冲器地址开始，然后从平面化图像的第二平面读取第二序列的视频数据缓冲区从第二个读指针指示的缓冲区地址开始。该装置包括地址生成单元和序列计数器。地址生成单元包括多个读指针，每个读指针被配置为指示视频缓冲器的不同数据平面内的存储器位置。地址单元被配置为寻址在由读取指针中的活动的一个指示的位置开始的视频缓冲器中的一系列存储器位置。序列计数器被配置为检测存储器位置序列的最终存储器位置何时已被地址生成单元寻址，并且作为响应，选择读取指针中的不同的一个作为活动读指针。

7. 发明授权

US6058440A Programmable and adaptive resource allocation device and resource use recorder 失效
标题翻译：可编程和自适应资源分配设备和资源使用记录器
公开(公告)号：US6058440A
公开(公告)日：2000-05-02
申请号：US926314
申请日：1997-09-05
申请人： Peter Bloch , Leonard W. Cross , Ali S. Oztaskin
发明人： Peter Bloch , Leonard W. Cross , Ali S. Oztaskin
IPC分类号： G06F13/42
CPC分类号： G06F13/4226
摘要： A method and device is provided for controlling access to a resource by a bus master over a bus coupling the bus master to the resource. The resource includes an intelligent component that controls the operation of the resource. A series of packets is transmitted over the bus between the bus master and the resource, at a transmission speed controlled by the bus master. A request/response logic in the resource controllably throttles transmissions of the packets at the resource, at specified time intervals. Each of the time intervals is set at a time period to assure sufficient time for the intelligent component to complete processing tasks contained in the packets.
摘要翻译：提供了一种方法和装置，用于通过总线主机将总线主机耦合到资源来控制总线主机对资源的访问。该资源包括一个控制资源操作的智能组件。在总线主机和资源之间的总线上，以总线主控制的传输速度传送一系列数据包。资源中的请求/响应逻辑以规定的时间间隔可控制地阻止资源处的分组的传输。每个时间间隔被设置在一个时间段，以确保智能组件足够的时间来完成包中包含的处理任务。

8. 发明授权

US06026473A Method and apparatus for storing data in a sequentially written memory using an interleaving mechanism 失效
标题翻译：使用交织机构将数据存储在顺序写入的存储器中的方法和装置
公开(公告)号：US06026473A
公开(公告)日：2000-02-15
申请号：US771847
申请日：1996-12-23
申请人： Leonard W. Cross , Edward Paul Wallace
发明人： Leonard W. Cross , Edward Paul Wallace
IPC分类号： G06F5/16 , G06F13/16 , G06F12/00 , G06F13/00
CPC分类号： G06F5/16 , G06F13/1647
摘要： A method and apparatus for storing data values received within respective cycle periods of a clock signal are disclosed. Data values are alternately stored in first and second data hold registers and then output by each data hold register for a time greater than a cycle period of the clock signal. Address values at which the incoming data values are to be written are alternately stored in first and second address hold registers. Data stored in the first data hold register is written to a latch-based memory element in a first memory bank indicated by an address value stored in the first address hold register. Data stored in the second data hold register is written to a latch-based memory element in a second memory bank indicated by an address value stored in the second address hold register.
摘要翻译：公开了一种用于存储在时钟信号的各个周期周期内接收的数据值的方法和装置。数据值交替存储在第一和第二数据保持寄存器中，然后由每个数据保持寄存器输出大于时钟信号周期的时间。输入数据值要被写入的地址值交替存储在第一和第二地址保持寄存器中。存储在第一数据保持寄存器中的数据被写入由存储在第一地址保持寄存器中的地址值指示的第一存储体中的基于锁存器的存储元件。存储在第二数据保持寄存器中的数据被写入由存储在第二地址保持寄存器中的地址值指示的第二存储体中的基于锁存器的存储元件。

9. 发明授权

US06618770B2 Graphics address relocation table (GART) stored entirely in a local memory of an input/output expansion bridge for input/output (I/O) address translation 失效
标题翻译：图形地址重定位表（GART）完全存储在用于输入/输出（I / O）地址转换的输入/输出扩展桥的本地存储器中
公开(公告)号：US06618770B2
公开(公告)日：2003-09-09
申请号：US10142706
申请日：2002-05-09
申请人： Raman Nayyar , Douglas R. Moran , Leonard W. Cross
发明人： Raman Nayyar , Douglas R. Moran , Leonard W. Cross
IPC分类号： G06F300
CPC分类号： G06F12/1081 , G06F13/404
摘要： A method and apparatus are provided for performing address translation in an input/output (I/O) expansion bridge. The I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit. The first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports. The first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system. The second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device. The address translation unit is coupled to the first interface unit and the second interface unit. The address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.
摘要翻译：提供一种用于在输入/输出（I / O）扩展桥中执行地址转换的方法和装置。 I / O扩展桥包括第一接口单元，第二接口单元和地址转换单元。第一接口单元被配置为通过一个或多个I / O端口耦合到系统存储器和I / O控制器。第一接口单元使得能够通过到计算机系统的主存储器的一个或多个I / O端口进行数据传输。第二接口单元提供总线控制信号和地址以使得能够通过总线向外部设备传输数据或从外部设备传送数据。地址转换单元耦合到第一接口单元和第二接口单元。地址转换单元通过访问包含计算机系统的主存储器中的页面的物理地址的本地存储器来翻译与在第二接口上接收到的事务相关联的地址。

10. 发明授权

US06457068B1 Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation 有权
标题翻译：图形地址重定位表（GART）完全存储在扩展桥的本地存储器中，用于地址转换
公开(公告)号：US06457068B1
公开(公告)日：2002-09-24
申请号：US09385209
申请日：1999-08-30
申请人： Raman Nayyar , Douglas R. Moran , Leonard W. Cross
发明人： Raman Nayyar , Douglas R. Moran , Leonard W. Cross
IPC分类号： G06F300
CPC分类号： G06F12/1081 , G06F13/404
摘要： A method and apparatus are provided for performing address translation in an input/output (I/O) expansion bridge. The I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit. The first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports. The first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system. The second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device. The address translation unit is coupled to the first interface unit and the second interface unit. The address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.
摘要翻译：提供一种用于在输入/输出（I / O）扩展桥中执行地址转换的方法和装置。 I / O扩展桥包括第一接口单元，第二接口单元和地址转换单元。第一接口单元被配置为通过一个或多个I / O端口耦合到系统存储器和I / O控制器。第一接口单元使得能够通过到计算机系统的主存储器的一个或多个I / O端口进行数据传输。第二接口单元提供总线控制信号和地址以使得能够通过总线向外部设备传输数据或从外部设备传送数据。地址转换单元耦合到第一接口单元和第二接口单元。地址转换单元通过访问包含计算机系统的主存储器中的页面的物理地址的本地存储器来翻译与在第二接口上接收的事务相关联的地址。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式