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1. 发明授权

US5982425A Method and apparatus for draining video data from a planarized video buffer 失效
标题翻译：从平面化视频缓冲器中排出视频数据的方法和装置
公开(公告)号：US5982425A
公开(公告)日：1999-11-09
申请号：US772701
申请日：1996-12-23
申请人： John Lewis Allen , Leonard W. Cross , Bill A. Munson , Ali S. Oztaskin , Roger Traylor
发明人： John Lewis Allen , Leonard W. Cross , Bill A. Munson , Ali S. Oztaskin , Roger Traylor
IPC分类号： H04N9/64 , H04N5/76 , H04N3/14
CPC分类号： H04N9/64
摘要： A method and apparatus for draining video data from a planarized video buffer in a video camera. The method includes the steps of reading a first sequence of video data from a first plane of the planarized image buffer starting at a buffer address indicated by a first pointer, and then reading a second sequence of video data from a second plane of the planarized image buffer starting at a buffer address indicated by a second read pointer. The apparatus includes an address generation unit and a sequence counter. The address generation unit includes a number of read pointers each configured to indicate a memory location within a different data plane of a video buffer. The address unit is configured to address a sequence of memory locations in a video buffer starting at a location indicated by an active one of the read pointers. The sequence counter is configured to detect when a final memory location of the sequence of memory locations has been addressed by the address generation unit and, in response, to select a different one of the read pointers to be the active read pointer.
摘要翻译：一种用于从视频摄像机中的平面化视频缓冲器排出视频数据的方法和装置。该方法包括从平坦化图像缓冲器的第一平面读取第一序列的视频数据的步骤，从由第一指针指示的缓冲器地址开始，然后从平面化图像的第二平面读取第二序列的视频数据缓冲区从第二个读指针指示的缓冲区地址开始。该装置包括地址生成单元和序列计数器。地址生成单元包括多个读指针，每个读指针被配置为指示视频缓冲器的不同数据平面内的存储器位置。地址单元被配置为寻址在由读取指针中的活动的一个指示的位置开始的视频缓冲器中的一系列存储器位置。序列计数器被配置为检测存储器位置序列的最终存储器位置何时已被地址生成单元寻址，并且作为响应，选择读取指针中的不同的一个作为活动读指针。

2. 发明授权

US5768626A Method and apparatus for servicing a plurality of FIFO's in a capture gate array 失效
标题翻译：用于在捕获门阵列中维护多个FIFO的方法和装置
公开(公告)号：US5768626A
公开(公告)日：1998-06-16
申请号：US874000
申请日：1997-06-13
申请人： Bill A. Munson , Ali S. Oztaskin
发明人： Bill A. Munson , Ali S. Oztaskin
IPC分类号： G06F5/06 , G06F13/00
CPC分类号： G06F5/06
摘要： The present invention provides a direct memory access unit for use in prioritizing the servicing of FIFO buffers in a capture gate array coupled to a video processing device. The capture gate array comprises at least a FIFO input unit having a plurality of FIFO buffers for receiving as input to the capture gate array separated Y, U and V bitmap data entries and a bus interface unit coupled to a video memory bus for outputting the data entries to the video processing device. The direct memory access unit preferably comprises at least a signal generation unit, a logic unit and a control unit. The signal generation unit receives as input from the FIFO unit depth values for the FIFO buffers representing the number of data entries currently stored in respective FIFO buffers in addition to comparators which compare the depth value of each FIFO buffer with at least first and second trip point values stored in at least first and second buffers. The trip point values represent predetermined numbers of data entries within the FIFO buffers, and the second trip point value is set so as to be greater in magnitude than the first trip point value. The signal generation unit then generates a first trip point signal for each FIFO buffer having a depth value equal to or greater than the first trip point value but less than the second trip point value and a second trip point signal for each FIFO buffer having a depth value equal to or greater than the second trip point value. The logic unit is coupled to the signal generation unit and comprises combinational logic for prioritizing the generated trip point signals associated with the respective FIFO buffers. The logic unit further generates FIFO service requests in accordance with the prioritized trip point signals.
摘要翻译：本发明提供了一种直接存储器访问单元，用于在耦合到视频处理设备的捕获门阵列中优先处理FIFO缓冲器的服务。捕获门阵列至少包括具有多个FIFO缓冲器的FIFO输入单元，用于接收作为捕获门阵列分离的Y，U和V位图数据条目的输入，以及耦合到视频存储器总线的总线接口单元，用于输出数据条目到视频处理设备。直接存储器访问单元优选地至少包括信号生成单元，逻辑单元和控制单元。信号生成单元除了比较每个FIFO缓冲器的深度值与至少第一和第二跳变点之间的比较器之外，还从表示当前存储在各个FIFO缓冲器中的数据条目数的FIFO缓冲器的FIFO单元的深度值接收来自FIFO单元的深度值存储在至少第一和第二缓冲器中的值。跳变点值表示FIFO缓冲器内的预定数量的数据项，并且第二跳变点值被设置为大于第一跳变点值。然后，信号生成单元为每个具有深度值等于或大于第一跳变点值但小于第二跳变点值的每个FIFO缓冲器产生第一跳变点信号，并且为每个具有深度的FIFO缓冲器产生第二跳变点信号值等于或大于第二跳变点值。逻辑单元耦合到信号产生单元，并且包括组合逻辑，用于对与各个FIFO缓冲器相关联的产生的跳变点信号进行优先排序。逻辑单元还根据优先跳变点信号产生FIFO服务请求。

3. 发明授权

US6058440A Programmable and adaptive resource allocation device and resource use recorder 失效
标题翻译：可编程和自适应资源分配设备和资源使用记录器
公开(公告)号：US6058440A
公开(公告)日：2000-05-02
申请号：US926314
申请日：1997-09-05
申请人： Peter Bloch , Leonard W. Cross , Ali S. Oztaskin
发明人： Peter Bloch , Leonard W. Cross , Ali S. Oztaskin
IPC分类号： G06F13/42
CPC分类号： G06F13/4226
摘要： A method and device is provided for controlling access to a resource by a bus master over a bus coupling the bus master to the resource. The resource includes an intelligent component that controls the operation of the resource. A series of packets is transmitted over the bus between the bus master and the resource, at a transmission speed controlled by the bus master. A request/response logic in the resource controllably throttles transmissions of the packets at the resource, at specified time intervals. Each of the time intervals is set at a time period to assure sufficient time for the intelligent component to complete processing tasks contained in the packets.
摘要翻译：提供了一种方法和装置，用于通过总线主机将总线主机耦合到资源来控制总线主机对资源的访问。该资源包括一个控制资源操作的智能组件。在总线主机和资源之间的总线上，以总线主控制的传输速度传送一系列数据包。资源中的请求/响应逻辑以规定的时间间隔可控制地阻止资源处的分组的传输。每个时间间隔被设置在一个时间段，以确保智能组件足够的时间来完成包中包含的处理任务。

4. 发明授权

US5838387A Digital video scaling engine 失效
标题翻译：数字视频缩放引擎
公开(公告)号：US5838387A
公开(公告)日：1998-11-17
申请号：US771300
申请日：1996-12-20
申请人： John L. Allen , Leonard W. Cross , Ali S. Oztaskin
发明人： John L. Allen , Leonard W. Cross , Ali S. Oztaskin
IPC分类号： G06T3/40 , H04N1/393 , H04N5/262 , G06F15/66
CPC分类号： G06T3/4023 , H04N1/3935 , H04N5/2628
摘要： A video scaling engine for scaling video data over a plurality of clock cycles is disclosed. In a first clock cycle of the plurality of clock cycles, a multiplier of the video scaling engine multiplies an input pixel by a coefficient indicated by a coefficient select signal to generate a first product. The first product is stored in an accumulator of the video scaling engine. In a second clock cycle of the plurality of clock cycles, the multiplier multiplies another input pixel by a coefficient indicated by another coefficient select signal to generate a second product. The second product is added to the contents of the accumulator to produce a sum including the first and second products. The sum including the first and second products is stored in the accumulator and then divided by a value based on at least one of the coefficients to produce a scaled output pixel.
摘要翻译：公开了一种用于在多个时钟周期上缩放视频数据的视频缩放引擎。在多个时钟周期的第一时钟周期中，视频缩放引擎的乘法器将输入像素乘以由系数选择信号指示的系数，以产生第一乘积。第一个产品存储在视频缩放引擎的累加器中。在多个时钟周期的第二时钟周期中，乘法器将另一个输入像素乘以由另一系数选择信号指示的系数，以产生第二乘积。将第二产品添加到蓄电池的内容物中以产生包括第一和第二产品的总和。包括第一和第二乘积的总和被存储在累加器中，然后根据系数中的至少一个被除以一个值以产生一个缩放的输出像素。

5. 发明授权

US6085325A Method and apparatus for supporting power conservation operation modes 失效
标题翻译：支持节电运行模式的方法和装置
公开(公告)号：US6085325A
公开(公告)日：2000-07-04
申请号：US766089
申请日：1996-12-16
申请人： David R. Jackson , Leonard W. Cross , Robert A. Jacobs , Ali S. Oztaskin
发明人： David R. Jackson , Leonard W. Cross , Robert A. Jacobs , Ali S. Oztaskin
IPC分类号： G06F1/04 , G06F1/08 , G06F1/32 , G06F13/38 , G06F1/26 , G06F1/28
CPC分类号： G06F1/3237 , G06F1/08 , G06F1/32 , G06F1/325 , Y02B60/1221
摘要： An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.
摘要翻译：描述了一种用于管理从总线接收电力的电子装置中的电力的装置。该装置包括时钟使能电路，其禁止产生从接收第一信号时由振荡器输出的原始频率导出的标称时钟频率的时钟。时间独立的时间参考电路耦合到时钟使能电路。时间独立的时间参考电路在接收到进入暂停状态的信号之后的第一预定时间段内将第一信号发送到时钟使能电路。

6. 发明授权

US07702826B2 Method and apparatus by utilizing platform support for direct memory access remapping by remote DMA (“RDMA”)-capable devices 有权
标题翻译：通过利用支持远程DMA（“RDMA”）功能的直接存储器访问重映射的平台支持的方法和装置
公开(公告)号：US07702826B2
公开(公告)日：2010-04-20
申请号：US11321272
申请日：2005-12-28
申请人： Ali S. Oztaskin , Rajesh S. Madukkarumukumana , Greg J. Regnier
发明人： Ali S. Oztaskin , Rajesh S. Madukkarumukumana , Greg J. Regnier
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： An apparatus and method related to performing Remote Direct Memory Access Request (“RDMA”) is presented. In one embodiment, the apparatus comprises Remote direct memory access (“RDMA”) logic that executes a direct memory access (“DMA”) request from the remote peer. The apparatus further comprising a protection checking logic to verify a key and a target address in the DMA request and conversion logic to convert the target address to an input/output virtual address (“IOVA”) if the conversion is required. The IOVA is to be translated to the host physical address by an address translation unit at another hardware subsystem.
摘要翻译：提出了一种与执行远程直接存储器访问请求（“RDMA”）有关的装置和方法。在一个实施例中，该装置包括执行来自远程对等体的直接存储器访问（“DMA”）请求的远程直接存储器访问（“RDMA”）逻辑。该装置还包括一个保护检查逻辑，用于验证DMA请求中的密钥和目标地址，以及如果需要转换，则转换逻辑将目标地址转换为输入/输出虚拟地址（“IOVA”）。 IOVA将由另一硬件子系统上的地址转换单元转换为主机物理地址。

7. 发明授权

US5897667A Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner 失效
标题翻译：用于以突发方式将从第一总线接收的数据以非突发方式传送到第二总线的方法和装置
公开(公告)号：US5897667A
公开(公告)日：1999-04-27
申请号：US755246
申请日：1996-11-22
申请人： Mark W. Miller , Ali S. Oztaskin
发明人： Mark W. Miller , Ali S. Oztaskin
IPC分类号： G06F13/40 , G06F12/02 , G06F9/26
CPC分类号： G06F13/4027
摘要： A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to create burst cycles on a second bus that has protocols that allow burst cycles such as a Peripheral Component Interconnect (PCI) bus.
摘要翻译：桥接逻辑采用非突发写入周期，其作为在第一总线上跟随相关数据字的地址一次出现，检测到连续的地址，并使用该信息在具有允许的协议的第二总线上创建突发周期突发周期，例如外围部件互连（PCI）总线。

8. 发明申请

US20140089444A1 METHODS, APPARATUS AND SYSTEMS FOR FACILITATING RDMA OPERATIONS WITH REDUCED DOORBELL RINGS 有权
标题翻译：方法，装备和系统，用于减少DOORBELL环的RDMA操作
公开(公告)号：US20140089444A1
公开(公告)日：2014-03-27
申请号：US13628771
申请日：2012-09-27
申请人： Vadim Makhervaks , Kenneth G. Keels , Brian S. Hausauer , Ali S. Oztaskin
发明人： Vadim Makhervaks , Kenneth G. Keels , Brian S. Hausauer , Ali S. Oztaskin
IPC分类号： G06F15/167
CPC分类号： G06F15/17331
摘要： Methods, apparatus and systems for reducing usage of Doorbell Rings in connection with RDMA operations. A portion of system memory is employed as a Memory-Mapped Input/Output (MMIO) address space configured to be accessed via a hardware networking device. A Send Queue (SQ) is stored in MMIO and is used to facilitate processing of Work Requests (WRs) that are written to SQ entries by software and read from the SQ via the hardware networking device. The software and logic in the hardware networking device employ pointers identifying locations in the SQ corresponding to a next write WR entry slot and last read WR entry slot that are implemented to enable WRs to be written to and read from the SQ during ongoing operations under which the SQ is not emptied such that doorbell rings to notify the hardware networking device that new WRs have been written to the SQ are not required.
摘要翻译：与RDMA操作相关的减少门铃环使用的方法，装置和系统。系统存储器的一部分被用作经配置以经由硬件网络设备访问的存储器映射输入/输出（MMIO）地址空间。发送队列（SQ）存储在MMIO中，用于促进通过软件写入SQ条目并通过硬件网络设备从SQ读取的工作请求（WR）的处理。硬件网络设备中的软件和逻辑采用标识SQ中相应于下一个写入WR入口时隙的位置的指针，以及最后读取的WR入口时隙，其被实现为使得在正在进行的操作期间将WR写入到SQ并从其读取， SQ不能清空，以致门铃振铃以通知硬件网络设备不会向SQ写入新的WR。

9. 发明授权

US06347362B1 Flexible event monitoring counters in multi-node processor systems and process of operating the same 有权
标题翻译：多节点处理器系统中的灵活事件监控计数器及其操作过程
公开(公告)号：US06347362B1
公开(公告)日：2002-02-12
申请号：US09221577
申请日：1998-12-29
申请人： Ioannis T. Schoinas , Ali S. Oztaskin
发明人： Ioannis T. Schoinas , Ali S. Oztaskin
IPC分类号： G06F1300
CPC分类号： G06F11/3072 , G06F11/3006 , G06F11/3037 , G06F11/348 , G06F12/08 , G06F12/122 , G06F2201/88
摘要： A flexible event monitoring counter apparatus and process are provided for a processor system including a plurality of nodes, each node having a processor and a portion of a total main memory of the processor system. One example of such a processor system is a Non-Uniform-Memory-Architecture (NUMA) system. In order to reduce the total number of counters necessary, the counter structure will track certain ones of a type of event which occur in the processor system, determined in accordance with a predetermined standard to be most interesting, while discarding other ones of the same type of event determined by the standard to be less interesting. In accordance with one embodiment, the type of event which is tracked or discarded can be page accesses to pages of the total main memory. The standard of most interesting events can be based on the pages which receive the most requests for remote access from a node other than the node where the requested page is located. The information regarding the most interesting events can be used, if desired, to make decisions regarding migration and/or replication of pages between the different nodes.
摘要翻译：为包括多个节点的处理器系统提供灵活的事件监视计数器装置和处理，每个节点具有处理器和处理器系统的总主存储器的一部分。这种处理器系统的一个例子是非均匀存储器架构（NUMA）系统。为了减少所需的计数器总数，计数器结构将跟踪在处理器系统中出现的某种类型的事件，其根据预定标准确定为最有趣，同时丢弃相同类型的其他类型由标准决定的事件不那么有趣。根据一个实施例，被跟踪或丢弃的事件的类型可以是对总主存储器的页面的页面访问。最有趣的事件的标准可以基于从除请求的页面所在的节点之外的节点接收到对远程访问的最多请求的页面。如果需要，可以使用关于最有趣事件的信息来做出关于不同节点之间的页面的迁移和/或复制的决定。

10. 发明授权

US07853957B2 Doorbell mechanism using protection domains 有权
标题翻译：门铃机制使用保护域
公开(公告)号：US07853957B2
公开(公告)日：2010-12-14
申请号：US11106824
申请日：2005-04-15
申请人： Hemal V. Shah , Gary Y. Tsao , Arturo L. Arizpe , Ali S. Oztaskin
发明人： Hemal V. Shah , Gary Y. Tsao , Arturo L. Arizpe , Ali S. Oztaskin
IPC分类号： G06F9/44
CPC分类号： G06F13/28 , H04L49/90
摘要： In accordance with certain other techniques, doorbell information is received. A doorbell structure address is decoded from the doorbell information. A first protection domain identifier is determined from the doorbell structure address. A resource context of a data structure is determined from the doorbell information. The resource context at the doorbell address is read to determine a second protection domain identifier. The first protection domain identifier and the second protection domain identifier are compared to determine whether to update the resource context of the doorbell structure.
摘要翻译：根据某些其他技术，接收门铃信息。门铃结构地址从门铃信息解码。第一保护域标识符是从门铃结构地址确定的。从门铃信息确定数据结构的资源上下文。读取门铃地址处的资源上下文以确定第二保护域标识符。比较第一保护域标识符和第二保护域标识符，以确定是否更新门铃结构的资源上下文。

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