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1. 发明授权

US5517754A Fabrication processes for monolithic electronic modules 失效
标题翻译：单片电子模块的制造工艺
公开(公告)号：US5517754A
公开(公告)日：1996-05-21
申请号：US252794
申请日：1994-06-02
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Wayne J. Howell
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Wayne J. Howell
IPC分类号： H01L21/28 , H01L21/98 , H01L25/065 , H05K3/34
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/24145 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , Y10S269/903 , Y10S269/909 , Y10S428/914 , Y10T29/49124 , Y10T29/49144 , Y10T428/14 , Y10T428/1438 , Y10T428/1481 , Y10T428/24942
摘要： This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.
摘要翻译：本发明包括用于在多个单片电子模块上同时形成表面金属化的各种高生产方法。每个单片电子模块可以包括单个半导体芯片或多个半导体芯片。该方法可以采用自动中断堆叠中不同电子模块之间的侧面金属化的工件。多个工件在电子模块之间的堆叠内交错。每个工件可以包括用于永久地结合到堆叠中的相邻电子模块的端面的转移层。该转移层可以包括绝缘层，金属化层，有源电路层或其任何组合。因此，可以同时提供多个电子模块的侧表面金属化的端面金属化。

2. 发明授权

US5309318A Thermally enhanced semiconductor chip package 失效
标题翻译：热增强半导体芯片封装
公开(公告)号：US5309318A
公开(公告)日：1994-05-03
申请号：US109016
申请日：1993-08-18
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Gordon A. Kelley, Jr. , Christopher P. Miller
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Gordon A. Kelley, Jr. , Christopher P. Miller
IPC分类号： H01L23/473 , H01L25/00 , H01L25/065 , H05K7/20
CPC分类号： H01L25/0657 , H01L23/473 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589 , H01L2924/0002
摘要： A structure and method is disclosed for cooling a semiconductor computer chip module. The semiconductor computer chip module is made up of a plurality of semiconductor chips bonded together In one aspect of the present invention every other chip is staggered such that recesses are formed between protruding edges of every other chip along two opposite faces of the chip module. The opposite faces with the staggered chips are capped and sealed so that coolant channels are formed between the recesses and the sealing caps. In another aspect, one face of the chip module is bonded by a plurality of connectors to a base. The base and chip module with connectors form a chamber. The chamber is sealed and an opening is made in the base to circulate coolant into and around the connectors of the base and up along the coolant channels which are in fluid communication with the base. Thermal vias are provided between selected connectors and the chip module to conduct heat from the chips of the module to the connectors.
摘要翻译：公开了用于冷却半导体计算机芯片模块的结构和方法。半导体计算机芯片模块由结合在一起的多个半导体芯片组成。在本发明的一个方面，每隔一个芯片交错，使得在芯片模块的两个相对面上的每个其他芯片的突出边缘之间形成凹槽。具有交错的芯片的相对面被封盖和密封，使得在凹部和密封盖之间形成冷却剂通道。另一方面，芯片模块的一个面通过多个连接器连接到基座。具有连接器的基座和芯片模块形成一个腔室。腔室被密封，并且在基座中形成开口，以使冷却剂沿着与底座流体连通的冷却剂通道向底部的连接器和连接器周围循环。在选定的连接器和芯片模块之间提供热通孔，以将热量从模块的芯片传导到连接器。

3. 发明授权

US5920101A Structure for making sub-lithographic images by the intersection of two spacers 失效
标题翻译：通过两个间隔物交叉制作亚光刻图像的结构
公开(公告)号：US5920101A
公开(公告)日：1999-07-06
申请号：US144806
申请日：1998-09-01
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , James M. Leas , Jack A. Mandelman
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , James M. Leas , Jack A. Mandelman
IPC分类号： H01L21/306 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L21/46 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer. Alternatively, the first and/or second pattern materials may be totally removed, left in place, or planarized
摘要翻译：一种形成由两个间隔物相交形成的亚光刻图像的方法。提供具有基本上垂直的侧壁的具有可选择性蚀刻材料的第一图案的衬底。第一侧壁间隔物由相对于第一图案材料可选择性蚀刻的材料形成。形成与第一图案相交的第二图案的可选择性蚀刻材料的第二图案。第二图案的侧壁也是基本垂直的。第二侧壁间隔件由相对于第二图案材料可选择地蚀刻的材料形成。蚀刻第二图案材料以离开第二侧壁间隔物。或者，第一和/或第二图案材料可以被完全去除，留在原位或平坦化

4. 发明授权

US5834818A Structure for making sub-lithographic images by the intersection of two spacers 失效
标题翻译：通过两个间隔物交叉制作亚光刻图像的结构
公开(公告)号：US5834818A
公开(公告)日：1998-11-10
申请号：US864836
申请日：1997-05-29
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , James M. Leas , Jack A. Mandelman
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , James M. Leas , Jack A. Mandelman
IPC分类号： H01L21/306 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L21/46 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer. Alternatively, the first and/or second pattern materials may be totally removed, left in place, or planarized.
摘要翻译：一种形成由两个间隔物相交形成的亚光刻图像的方法。提供具有基本上垂直的侧壁的具有可选择性蚀刻材料的第一图案的衬底。第一侧壁间隔物由相对于第一图案材料可选择性蚀刻的材料形成。形成与第一图案相交的第二图案的可选择性蚀刻材料的第二图案。第二图案的侧壁也是基本垂直的。第二侧壁间隔件由相对于第二图案材料可选择地蚀刻的材料形成。蚀刻第二图案材料以离开第二侧壁间隔物。或者，第一和/或第二图案材料可以被完全去除，留在原位或平坦化。

5. 发明授权

US5596226A Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module 失效
标题翻译：具有芯片金属层和由相同金属组成的转移金属层的半导体芯片及相应的电子模块
公开(公告)号：US5596226A
公开(公告)日：1997-01-21
申请号：US301290
申请日：1994-09-06
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Timothy H. Daubenspeck , Wayne J. Howell
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Timothy H. Daubenspeck , Wayne J. Howell
IPC分类号： H01L25/18 , H01L21/02 , H01L21/301 , H01L21/3205 , H01L21/822 , H01L21/98 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/04 , H01L23/48
CPC分类号： H01L25/50 , H01L24/24 , H01L25/0657 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/14
摘要： A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.
摘要翻译：一种制造方法，包括半导体芯片切痕工艺以及由此形成的半导体芯片和电子模块。制造方法包括提供包括多个集成电路芯片的晶片，其中它们之间具有切口区域。芯片金属化存在于切口区域内。使用光刻工艺来保护仅暴露切口区域的晶片。接下来，蚀刻晶片，从切口区域清除芯片金属化。然后切割晶片，并且将芯片堆叠以形成单片电子模块。处理电子模块的侧表面以暴露延伸到其上的转移金属，从而便于与电子模块内的芯片的电连接。阐述了制造方法的具体细节，所得到的集成电路芯片和单片电子模块。

6. 发明授权

US5466634A Electronic modules with interconnected surface metallization layers and fabrication methods therefore 失效
标题翻译：因此，具有互连表面金属化层的电子模块和制造方法
公开(公告)号：US5466634A
公开(公告)日：1995-11-14
申请号：US359982
申请日：1994-12-20
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
IPC分类号： H01L23/538 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/44
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/24145 , H01L2224/48091 , H01L2224/49109 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/30107
摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.
摘要翻译：阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。所述方法包括提供包括多个堆叠的IC芯片的堆叠。在堆叠上形成侧面薄膜金属化层。接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

7. 发明授权

US5426566A Multichip integrated circuit packages and systems 失效
标题翻译：多芯片集成电路封装和系统
公开(公告)号：US5426566A
公开(公告)日：1995-06-20
申请号：US826
申请日：1993-01-04
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Howard L. Kalter , Gordon A. Kelley, Jr. , Christopher P. Miller , Dale E. Pontius , Willem B. van der Hoeven , Steven Platt
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Howard L. Kalter , Gordon A. Kelley, Jr. , Christopher P. Miller , Dale E. Pontius , Willem B. van der Hoeven , Steven Platt
IPC分类号： H01L23/52 , H01L25/065 , H05K7/00
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06596 , H01L2924/0002 , H01L2924/16195
摘要： Multichip integrated circuit packages and systems of multichip packages having reduced interconnecting lead lengths are disclosed. The multichip package includes a multiplicity of semiconductor chip layers laminated together in a unitized module. A first metallization pattern is connected to the integrated circuit chips on at least one side surface of the unitized module. In addition, at least one end surface of the module contains a second metallization pattern which is configured to facilitate connection of the package to an external signal source, such as another multichip package. The system includes at least two such packages which are electrically coupled via either metallization patterns provided on the end surface of the packagers. If required, a plurality of multichip packages can be directly coupled into the system in an analogous manner. Further specific details of the multichip package and the system of multichip packages are set forth herein.
摘要翻译：公开了具有减小的互连引线长度的多芯片集成电路封装和多芯片封装的系统。多芯片封装包括在单元化模块中层叠在一起的多个半导体芯片层。第一金属化图案在集成模块的至少一个侧表面上连接到集成电路芯片。此外，模块的至少一个端面包含第二金属化图案，其被配置为便于将封装件连接到诸如另一多芯片封装的外部信号源。该系统包括至少两个这样的包装，其经由设置在包装机的端面上的金属化图案电耦合。如果需要，可以以类似的方式将多个多芯片封装直接耦合到系统中。本文阐述了多芯片封装和多芯片封装系统的进一步具体细节。

8. 发明授权

US5055898A DRAM memory cell having a horizontal SOI transfer device disposed over a buried storage node and fabrication methods therefor 失效
标题翻译： DRAM存储单元具有设置在掩埋存储节点上的水平SOI转移装置及其制造方法
公开(公告)号：US5055898A
公开(公告)日：1991-10-08
申请号：US693880
申请日：1991-04-30
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John R. Pessetto , Francis R. White
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John R. Pessetto , Francis R. White
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/08 , H01L27/10 , H01L27/108 , H01L29/786
CPC分类号： H01L27/10844 , H01L27/10832 , H01L29/78603 , H01L29/78654
摘要： A semiconductor memory cell, and methods of fabricating same, that includes a substrate (10) and a plurality of trench capacitors (12) formed at least partially within the substrate and dielectrically isolated therefrom. A silicon-on-insulator (SOI) region includes a silicon layer (16) that overlies an insulator (14). The silicon layer is differentiated into a plurality of active device regions, each of which is disposed above one of the electrically conductive regions. Each of the active device regions is coupled to an overlying first electrode, or wordline (20), for forming a gate node of an access transistor (1), to a second electrode, or bitline (32), for forming a source node of the access transistor, and to the underlying trench capacitor for forming a drain node of the access transistor. The wordline includes a pair of opposed, electrically insulating vertical sidewalls, and the source node and the drain node of each of the access transistors are each comprised of an electrical conductor disposed upon one of the vertical sidewalls. The array of memory cells further includes structure (11, 13) for coupling the active device regions to the substrate to reduce or eliminate a floating substrate effect.
摘要翻译：一种半导体存储单元及其制造方法，其包括基板（10）和至少部分地形成在基板内并与之介电隔离的多个沟槽电容器（12）。绝缘体上硅（SOI）区域包括覆盖绝缘体（14）的硅层（16）。硅层被区分成多个有源器件区域，每个有源器件区域设置在一个导电区域之上。每个有源器件区域耦合到上覆的第一电极或用于形成存取晶体管（1）的栅极节点的字线（20），到第二电极或位线（32），用于形成源节点存取晶体管，以及用于形成存取晶体管的漏极节点的底层沟槽电容器。字线包括一对相对的，电绝缘的垂直侧壁，并且每个存取晶体管的源极节点和漏极节点各自包括设置在垂直侧壁中的一个上的电导体。存储单元阵列还包括用于将有源器件区域耦合到衬底的结构（11,13），以减少或消除浮置衬底效应。

9. 发明授权

US4276095A Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations 失效
标题翻译：制造具有降低的阈值电压对源极与基板电压变化的灵敏度的MOSFET器件的方法
公开(公告)号：US4276095A
公开(公告)日：1981-06-30
申请号：US19797
申请日：1979-03-12
申请人： Kenneth E. Beilstein, Jr. , Harish N. Kotecha
发明人： Kenneth E. Beilstein, Jr. , Harish N. Kotecha
IPC分类号： H01L21/265 , H01L29/78 , H01L21/26
CPC分类号： H01L21/26513 , H01L29/7838
摘要： A MOSFET device structure is disclosed where the channel region has formed therein a buried layer of dopant of the same conductivity type as the source and drain, so that the depletion layers for the PN junctions at the upper and lower boundaries thereof intersect in the middle of the implanted region, effectively forming a buried insulator layer between the source and drain. The presence of this layer increases the distance between the mirrored electrostatic charges in the gate and in the bulk of the substrate beneath the MOSFET, thereby reducing the sensitivity of the threshold voltage of the device to variations in the source to substrate voltage.
摘要翻译：公开了MOSFET器件结构，其中沟道区域在其中形成与源极和漏极相同的导电类型的掺杂剂的掩埋层，使得在其上部和下部边界处的PN结的耗尽层在注入区域，有效地在源极和漏极之间形成掩埋绝缘体层。该层的存在增加了栅极中的镜像静电电荷和MOSFET下面的衬底体中的镜像静电电荷之间的距离，从而降低了器件的阈值电压对源极与衬底电压变化的灵敏度。

10. 发明授权

US5517057A Electronic modules with interconnected surface metallization layers 失效
标题翻译：具有互连表面金属化层的电子模块
公开(公告)号：US5517057A
公开(公告)日：1996-05-14
申请号：US451356
申请日：1995-05-26
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
IPC分类号： H01L23/538 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L23/48 , H01L23/522
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/24145 , H01L2224/48091 , H01L2224/49109 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/30107
摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.
摘要翻译：阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。所述方法包括提供包括多个堆叠的IC芯片的堆叠。在堆叠上形成侧面薄膜金属化层。接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

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