专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07949980B1 Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities 有权
标题翻译：电路设计工具支持具有实时锁相环重配置能力的设备
公开(公告)号：US07949980B1
公开(公告)日：2011-05-24
申请号：US12184223
申请日：2008-07-31
申请人： Ian Eu Meng Chan , Kumara Tharmalingam
发明人： Ian Eu Meng Chan , Kumara Tharmalingam
IPC分类号： G06F17/50 , G06F15/177 , G06F9/00
CPC分类号： G06F17/5054 , G06F17/505 , H03L7/08
摘要： Computer-aided-design tools are provided that support real-time phase-locked loop reconfiguration with a single design compilation. Each design compilation may involve operations such as logic synthesis and place and route operations. A circuit designer who is designing an integrated circuit may supply circuit design data. The circuit design data may include design data for multiple configurations of a phase-locked loop. By using a phase-locked loop scan chain initialization file generator engine located in a CAD tool design input wizard, the computer-aided-design tools may produce multiple phase-locked loop initialization files without performing a design compilation. The CAD tools may process one or more initialization files and the circuit design data to produce output data. The output data may include configuration data to implement the circuit design. The output data may also include warning messages that indicate when phase-locked loop settings in an initialization file do not match settings in the circuit design.
摘要翻译：提供了计算机辅助设计工具，通过单一设计编译支持实时锁相环重新配置。每个设计编译可能涉及诸如逻辑综合和放置和路由操作之类的操作。设计集成电路的电路设计者可以提供电路设计数据。电路设计数据可以包括用于锁相环的多个配置的设计数据。通过使用位于CAD工具设计输入向导中的锁相环扫描链初始化文件生成器引擎，计算机辅助设计工具可以产生多个锁相环初始化文件，而不执行设计编译。 CAD工具可以处理一个或多个初始化文件和电路设计数据以产生输出数据。输出数据可以包括用于实现电路设计的配置数据。输出数据还可以包括警告消息，其指示初始化文件中的锁相环设置与电路设计中的设置不匹配。

2. 发明申请

US20050187998A1 Multiplier-accumulator block mode splitting 有权
标题翻译：乘法器 - 累加器块模式分割
公开(公告)号：US20050187998A1
公开(公告)日：2005-08-25
申请号：US10783820
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
IPC分类号： G06F7/544 , G06F15/00 , H03K19/177
CPC分类号： G06F7/5443 , H03K19/17732
摘要： A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.
摘要翻译：提供了一种可编程逻辑器件，其包括具有模式分离能力的MAC块。可以同时实现不同的操作模式，从而可以在不同的操作模式之间分配MAC块的乘法器和其它DSP电路。例如，可以使用一个乘法器来实现乘法模式，而另外两个乘法器可以用于实现两个乘法器模式的和。

3. 发明授权

US09559881B2 Transceiver system with reduced latency uncertainty 有权
标题翻译：收发器系统具有降低的延迟不确定性
公开(公告)号：US09559881B2
公开(公告)日：2017-01-31
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
IPC分类号： H04L7/00 , H04B1/38 , H04L25/14
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译：描述了具有降低的等待时间不确定性的收发机系统。在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

4. 发明授权

US08386553B1 Large multiplier for programmable logic device 有权
公开(公告)号：US08386553B1
公开(公告)日：2013-02-26
申请号：US11682787
申请日：2007-03-06
申请人： Martin Langhammer , Kumara Tharmalingam
发明人： Martin Langhammer , Kumara Tharmalingam
IPC分类号： G06F7/52
CPC分类号： G06F17/10 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.

5. 发明授权

US08001537B1 Method and apparatus for compiling programmable logic device configurations 有权
标题翻译：用于编译可编程逻辑器件配置的方法和装置
公开(公告)号：US08001537B1
公开(公告)日：2011-08-16
申请号：US11294702
申请日：2005-12-05
申请人： Mihail Iotov , David Neto , Pouyan Djahani , David Karchmer , Kumara Tharmalingam
发明人： Mihail Iotov , David Neto , Pouyan Djahani , David Karchmer , Kumara Tharmalingam
IPC分类号： G06F9/45 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5054 , G06F8/76
摘要： During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.
摘要翻译：在第一类型的可编程逻辑器件（例如，FPGA）中的用户逻辑设计的编译期间，在进行选择的至少一些步骤中保留原木。当该逻辑设计迁移到另一种类型的可编程逻辑器件（例如，掩码可编程逻辑器件）时，记录的步骤被考虑以确保进行相同的选择，使得目标器件在功能上等同于原装置

6. 发明授权

US07437401B2 Multiplier-accumulator block mode splitting 有权
标题翻译：乘法器 - 累加器块模式分割
公开(公告)号：US07437401B2
公开(公告)日：2008-10-14
申请号：US10783820
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
IPC分类号： G06F7/48
CPC分类号： G06F7/5443 , H03K19/17732
摘要： A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.
摘要翻译：提供了一种可编程逻辑器件，其包括具有模式分离能力的MAC块。可以同时实现不同的操作模式，从而可以在不同的操作模式之间分配MAC块的乘法器和其它DSP电路。例如，可以使用一个乘法器来实现乘法模式，而另外两个乘法器可以用于实现两个乘法器模式的和。

7. 发明授权

US07082592B1 Method for programming programmable logic device having specialized functional blocks 失效
标题翻译：用于编程具有专门功能块的可编程逻辑器件的方法
公开(公告)号：US07082592B1
公开(公告)日：2006-07-25
申请号：US10463688
申请日：2003-06-16
申请人： Kumara Tharmalingam
发明人： Kumara Tharmalingam
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A programming method efficiently programs programmable logic devices of the type having specialized functional blocks. Those blocks may include multipliers and other arithmetic function elements, or may be various types of memory blocks. In order to efficiently program devices having such specialized functional blocks, without using a larger device than necessary, and without failing to fit a user design to a device, if the programming method finds that that there are more functions to be performed in specialized functional blocks than there are specialized functional blocks available, the programming method attempts to map some of the specialized functions to generic programmable logic elements (or other resources), assuming there are sufficient programmable logic elements (or other resources) that otherwise would remain unused in the user design.
摘要翻译：编程方法有效地编程具有专用功能块的类型的可编程逻辑器件。这些块可以包括乘法器和其他算术功能元件，或者可以是各种类型的存储器块。为了有效地对具有这种专门的功能块的设备进行编程，而不需要使用比必要的更大的设备，并且在不将用户设计适合于设备的情况下，如果编程方法发现在专用功能块中有更多的功能要执行比起可用的专用功能块，编程方法尝试将一些专用功能映射到通用可编程逻辑元件（或其他资源），假设有足够的可编程逻辑元件（或其他资源），否则将在用户中保持未使用设计。

8. 发明申请

US20050187997A1 Flexible accumulator in digital signal processing circuitry 失效
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US20050187997A1
公开(公告)日：2005-08-25
申请号：US10783789
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit. The least significant bits (LSBs) can be tied to ground and sent along the feedback path. To initialize the accumulator value, the MSBs of the initialization value can be input to the MAC block and sent directly to the add-subtract-accumulate unit. The LSBs can be sent to another multiplier that performs a multiply-by-one operation before being sent to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。最低有效位（LSB）可以连接到地并沿反馈路径发送。要初始化累加器值，初始化值的MSB可以输入到MAC块，并直接发送到加减法累加单元。可以将LSB发送到另一个乘法器，该乘法器在发送到加减法累加单元之前执行乘法运算。

9. 发明授权

US09170775B2 Flexible accumulator in digital signal processing circuitry 有权
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US09170775B2
公开(公告)日：2015-10-27
申请号：US12683686
申请日：2010-01-07
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

10. 发明授权

US08228102B1 Phase-locked loop architecture and clock distribution system 有权
标题翻译：锁相环架构和时钟分配系统
公开(公告)号：US08228102B1
公开(公告)日：2012-07-24
申请号：US12717062
申请日：2010-03-03
申请人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
发明人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
IPC分类号： H03L7/06
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条侧。可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。每个PMA三元组模块包括第一，第二和第三通道。第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。还公开了其它实施例和特征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式