专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08615543B1 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US08615543B1
公开(公告)日：2013-12-24
申请号：US13166119
申请日：2011-06-22
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

2. 发明授权

US07660841B2 Flexible accumulator in digital signal processing circuitry 失效
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US07660841B2
公开(公告)日：2010-02-09
申请号：US10783789
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

3. 发明授权

US07619451B1 Techniques for compensating delays in clock signals on integrated circuits 有权
标题翻译：补偿集成电路时钟信号延迟的技术
公开(公告)号：US07619451B1
公开(公告)日：2009-11-17
申请号：US11670971
申请日：2007-02-03
申请人： Tim Tri Hoang , Sergey Shumarayev , Kazi Asaduzzaman , Wanli Chang , Mian Z. Smith , Kang-Wei Lai , Leon Zheng
发明人： Tim Tri Hoang , Sergey Shumarayev , Kazi Asaduzzaman , Wanli Chang , Mian Z. Smith , Kang-Wei Lai , Leon Zheng
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , G06F1/12 , H03L7/081 , H03L7/0812
摘要： Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.
摘要翻译：提供了用于补偿由集成电路上的锁相环和延迟锁定环路产生的时钟信号中的相位和定时延迟的技术。耦合在锁定电路的反馈回路中的电路元件可以补偿输入引脚和输出引脚之间的定时和相位延迟。耦合在锁定电路的反馈环路中的其它电路元件可以补偿输入引脚和目的地电路元件之间的延迟。耦合在锁定电路的输入参考路径中的其他电路元件保留输入时钟和输入数据信号之间的定时关系。在目的地电路元件处接收的时钟信号和数据信号在输入引脚的输入时钟和输入数据信号之间具有相同的相位和定时关系。

4. 发明授权

US07467176B2 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US07467176B2
公开(公告)日：2008-12-16
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在乘法累加（MAC）块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

5. 发明授权

US08619931B1 Multi-purpose phase-locked loop for low cost transceiver 有权
标题翻译：用于低成本收发器的多功能锁相环
公开(公告)号：US08619931B1
公开(公告)日：2013-12-31
申请号：US12622152
申请日：2009-11-19
申请人： Tien Duc Pham , Sergey Shumarayev , Tim Tri Hoang , Thungoc M. Tran , Vinh Van Ho , Leon Zheng
发明人： Tien Duc Pham , Sergey Shumarayev , Tim Tri Hoang , Thungoc M. Tran , Vinh Van Ho , Leon Zheng
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H04L7/002
摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.
摘要翻译：提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

6. 发明授权

US07698358B1 Programmable logic device with specialized functional block 有权
标题翻译：具有专门功能块的可编程逻辑器件
公开(公告)号：US07698358B1
公开(公告)日：2010-04-13
申请号：US10746448
申请日：2003-12-24
申请人： Martin Langhammer , Leon Zheng , Chiao Kai Hwang , Gregory Starr
发明人： Martin Langhammer , Leon Zheng , Chiao Kai Hwang , Gregory Starr
IPC分类号： G06F7/38
CPC分类号： G06F7/5324
摘要： In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.
摘要翻译：在具有包含乘法器和加法器的专用功能块的可编程逻辑器件中，不能完全适合于可用乘法器的乘法运算部分地在专用功能块的乘法器中部分执行，并且部分地在可编程逻辑器件的可编程逻辑中配置的乘法器。专业功能块的未使用资源（包括加法器）可用于将专门功能块内部和外部生成的部分产品加在一起。在可编程逻辑器件的可编程逻辑中配置的一些加法器也可以用于该目的。

7. 发明授权

US07555667B1 Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry 有权
标题翻译：具有动态相位对准功能和共享锁相环电路的可编程逻辑器件集成电路
公开(公告)号：US07555667B1
公开(公告)日：2009-06-30
申请号：US11488365
申请日：2006-07-17
申请人： Ali Burney , Yu Xu , Leon Zheng , Sanjay K. Charagulla
发明人： Ali Burney , Yu Xu , Leon Zheng , Sanjay K. Charagulla
IPC分类号： G06F1/04 , G06F1/06
CPC分类号： H03K19/17716 , G06F1/12
摘要： Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.
摘要翻译：为可编程集成电路提供可调收发器电路。收发器电路具有可用于对准时钟和数据信号的动态相位对准电路。收发器电路支持锁相环源同步模式，该模式可用于从通过公共时钟计时的集成电路的发送接收数据。每个发送集成电路通过总线发送时钟和相关联的数据信号。收发器电路使用主从架构。每个收发器中的主动态相位对准电路接收该总线的时钟，并选择相应的最佳时钟相位，用于从多相时钟接收总线的输入数据。每个收发器中的主动态相位对准电路将最佳时钟相位分配给相关的从动态相位对准电路。只需要单个锁相环电路来产生多相时钟。

8. 发明申请

US20050187999A1 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US20050187999A1
公开(公告)日：2005-08-25
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/499 , G06F7/52 , G06F7/523 , G06F7/544
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

9. 发明授权

US09170775B2 Flexible accumulator in digital signal processing circuitry 有权
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US09170775B2
公开(公告)日：2015-10-27
申请号：US12683686
申请日：2010-01-07
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

10. 发明授权

US08364738B1 Programmable logic device with specialized functional block 有权
标题翻译：具有专门功能块的可编程逻辑器件
公开(公告)号：US08364738B1
公开(公告)日：2013-01-29
申请号：US12715645
申请日：2010-03-02
申请人： Martin Langhammer , Leon Zheng , Chiao Kai Hwang , Gregory Starr
发明人： Martin Langhammer , Leon Zheng , Chiao Kai Hwang , Gregory Starr
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F7/5324
摘要： In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.
摘要翻译：在具有包含乘法器和加法器的专用功能块的可编程逻辑器件中，不能完全适合于可用乘法器的乘法运算部分地在专用功能块的乘法器中部分地执行，并且部分地在可编程逻辑器件的可编程逻辑中配置的乘法器。专业功能块的未使用资源（包括加法器）可用于将专门功能块内部和外部生成的部分产品加在一起。在可编程逻辑器件的可编程逻辑中配置的一些加法器也可以用于该目的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式