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1. 发明授权

US08001537B1 Method and apparatus for compiling programmable logic device configurations 有权
标题翻译：用于编译可编程逻辑器件配置的方法和装置
公开(公告)号：US08001537B1
公开(公告)日：2011-08-16
申请号：US11294702
申请日：2005-12-05
申请人： Mihail Iotov , David Neto , Pouyan Djahani , David Karchmer , Kumara Tharmalingam
发明人： Mihail Iotov , David Neto , Pouyan Djahani , David Karchmer , Kumara Tharmalingam
IPC分类号： G06F9/45 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5054 , G06F8/76
摘要： During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.
摘要翻译：在第一类型的可编程逻辑器件（例如，FPGA）中的用户逻辑设计的编译期间，在进行选择的至少一些步骤中保留原木。当该逻辑设计迁移到另一种类型的可编程逻辑器件（例如，掩码可编程逻辑器件）时，记录的步骤被考虑以确保进行相同的选择，使得目标器件在功能上等同于原装置

2. 发明授权

US08161469B1 Method and apparatus for comparing programmable logic device configurations 有权
标题翻译：用于比较可编程逻辑器件配置的方法和装置
公开(公告)号：US08161469B1
公开(公告)日：2012-04-17
申请号：US11302568
申请日：2005-12-13
申请人： Mihail Iotov , Erhard Joachim Pistorius , Jim Park , David Karchmer
发明人： Mihail Iotov , Erhard Joachim Pistorius , Jim Park , David Karchmer
IPC分类号： G06F9/45
CPC分类号： G06F17/504 , G06F17/5054
摘要： Compiled configuration files for different programmable logic devices that are intended to be functionally equivalent may be compared using multiple different comparisons to assure functional equivalence. The different comparisons include a fitter or resource report comparison, an engineering bit settings report that compares vectors of bits that represent the settings of hard logic blocks, and comparisons based on location, connectivity and functionality. These comparisons are particularly well-suited for determining equivalence between different models of programmable logic devices, or even different types of devices such as field-programmable gate arrays as compared to mask-programmable logic devices.
摘要翻译：可以使用多个不同的比较来比较旨在功能等同的不同可编程逻辑器件的编译配置文件，以确保功能等同性。不同的比较包括装配者或资源报告比较，工程位设置报告，比较表示硬逻辑块设置的位的向量，以及基于位置，连接和功能的比较。与掩模可编程逻辑器件相比，这些比较特别适合于确定不同型号的可编程逻辑器件或甚至不同类型的器件（例如现场可编程门阵列）之间的等效性。

3. 发明申请

US20060236293A1 Method and apparatus for comparing and synchronizing programmable logic device user configuration dataset versions 有权
标题翻译：用于比较和同步可编程逻辑器件用户配置数据集版本的方法和装置
公开(公告)号：US20060236293A1
公开(公告)日：2006-10-19
申请号：US11108370
申请日：2005-04-18
申请人： Jim Park , Mihail Iotov , Michael Wenzler
发明人： Jim Park , Mihail Iotov , Michael Wenzler
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , Y10S707/99953 , Y10S707/99954
摘要： A graphical tool assists a user in migrating programming changes from one programmable logic device to another. The tool preferably compares a new user configuration dataset (e.g., the user configuration dataset including old features as well as newly-added features) for the “origin” programmable logic device to the existing user configuration dataset (i.e., the user configuration dataset including only old features) for a “destination” programmable logic device, and displays differences to the user. The tool preferably also assists the user to synchronize the devices by “copying” the new features of the user configuration dataset for one device into the old user configuration dataset for another device to the extent possible, by providing graphical inputs to allow the user to indicate which features should be synchronized, or to graphically manipulate the feature assignments directly.
摘要翻译：图形工具可帮助用户将编程变更从一个可编程逻辑器件迁移到另一个可编程逻辑器件。该工具优选地将用于“原始”可编程逻辑器件的新用户配置数据集（例如，包括旧特征以及新增功能的用户配置数据集）与现有用户配置数据集（即，仅包括用户配置数据集旧功能）用于“目的地”可编程逻辑设备，并显示与用户的差异。该工具优选地还通过提供图形输入来允许用户指示，通过将一个设备的用户配置数据集的新特征“复制”到另一设备的旧用户配置数据集中来帮助用户同步设备哪些特征应该同步，或直接图形地操作特征分配。

4. 发明申请

US20050088867A1 System and method for design entry and synthesis in programmable logic devices 有权
标题翻译：用于可编程逻辑器件中设计输入和合成的系统和方法
公开(公告)号：US20050088867A1
公开(公告)日：2005-04-28
申请号：US10353816
申请日：2003-01-28
申请人： Mihail Iotov , Greg Starr
发明人： Mihail Iotov , Greg Starr
IPC分类号： G11C27/00 , H03K19/177 , H03L7/089 , H03L7/093 , H03L7/183
CPC分类号： H03K19/17732 , G11C27/00 , H03L7/0891 , H03L7/093 , H03L7/183
摘要： A system and method facilitates the implementation of analog circuitry in electronic programmable devices. A user can specify user measurable parameters for analog features of the circuit, without requiring knowledge of the internal way in which those analog circuit are implemented in the programmable device to achieve desired properties of the analog parameters of interest. The implementation can be performed in different devices which may implement the analog circuit in vastly different ways.
摘要翻译：一种系统和方法有助于在电子可编程器件中实现模拟电路。用户可以为电路的模拟特征指定用户可测量的参数，而不需要知道在可编程设备中实现那些模拟电路的内部方式以获得感兴趣的模拟参数的所需属性。该实现可以在可以以非常不同的方式实现模拟电路的不同设备中执行。

5. 发明授权

US07487485B2 Methods and apparatus for design entry and synthesis of digital circuits 有权
标题翻译：数字电路设计输入和合成的方法和装置
公开(公告)号：US07487485B2
公开(公告)日：2009-02-03
申请号：US11473848
申请日：2006-06-23
申请人： Mihail Iotov
发明人： Mihail Iotov
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Methods and apparatus are provided for design entry and synthesis of components, such as components implemented on a programmable chip. In one example, a design tool receives natural or intuitive parameters describing characteristics of a component in a design. Natural or intuitive parameters include input data rate, output latency, footprint, etc. Non-natural or non-intuitive parameters such as clock rate and pipeline stages need not be provided. The design tool automatically selects optimal components using natural parameters. Multiple instantiations of an optimal component, or multiplexing through an optimal component can be used to further improve the design.
摘要翻译：提供了用于设计输入和组合部件的方法和装置，例如在可编程芯片上实现的部件。在一个示例中，设计工具接收描述设计中组件特征的自然或直观参数。自然或直观的参数包括输入数据速率，输出延迟，占位面积等。不需要提供诸如时钟频率和流水线阶段之类的非自然或非直观参数。设计工具使用自然参数自动选择最佳组件。可以使用最佳组件的多个实例，或通过最佳组件复用，以进一步改进设计。

6. 发明申请

US20060242616A1 Methods and apparatus for design entry and synthesis of digital circuits 有权
公开(公告)号：US20060242616A1
公开(公告)日：2006-10-26
申请号：US11473848
申请日：2006-06-23
申请人： Mihail Iotov
发明人： Mihail Iotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods and apparatus are provided for design entry and synthesis of components, such as components implemented on a programmable chip. In one example, a design tool receives natural or intuitive parameters describing characteristics of a component in a design. Natural or intuitive parameters include input data rate, output latency, footprint, etc. Non-natural or non-intuitive parameters such as clock rate and pipeline stages need not be provided. The design tool automatically selects optimal components using natural parameters. Multiple instantiations of an optimal component, or multiplexing through an optimal component can be used to further improve the design.

7. 发明授权

US07080345B1 Methods and apparatus for design entry and synthesis of digital circuits 失效
公开(公告)号：US07080345B1
公开(公告)日：2006-07-18
申请号：US10687192
申请日：2003-10-15
申请人： Mihail Iotov
发明人： Mihail Iotov
IPC分类号： G06F17/50 , G06F9/45 , H03K19/00
CPC分类号： G06F17/5045
摘要： Methods and apparatus are provided for design entry and synthesis of components, such as components implemented on a programmable chip. In one example, a design tool receives natural or intuitive parameters describing characteristics of a component in a design. Natural or intuitive parameters include input data rate, output latency, footprint, etc. Non-natural or non-intuitive parameters such as clock rate and pipeline stages need not be provided. The design tool automatically selects optimal components using natural parameters. Multiple instantiations of an optimal component, or multiplexing through an optimal component can be used to further improve the design.

8. 发明授权

US07992119B1 Real-time background legality verification of pin placement 有权
标题翻译：针脚放置的实时背景合法性验证
公开(公告)号：US07992119B1
公开(公告)日：2011-08-02
申请号：US12134999
申请日：2008-06-06
申请人： Mihail Iotov , Kamal Patel , Michael V. Wenzler
发明人： Mihail Iotov , Kamal Patel , Michael V. Wenzler
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Pin placement legality is verified in real-time in a background to reduce a number of input/output assignment analysis runs during a physical design of a programmable logic device. Edited pin properties are checked quickly in the background against certain rules, and results displayed to a user usually before a new pin is edited. Available and legal positions are found and displayed for a selected pin to reduce errors.
摘要翻译：引脚放置合法性在后台被实时验证，以减少在可编程逻辑器件的物理设计期间的多个输入/输出分配分析运行。编辑的针脚属性在背景中根据某些规则快速检查，并且结果通常在新的引脚编辑之前显示给用户。找到并显示所选引脚的可用和合法位置以减少错误。

9. 发明授权

US07580037B1 Techniques for graphical analysis and manipulation of circuit timing requirements 有权
标题翻译：图形分析和电路时序要求的操作技术
公开(公告)号：US07580037B1
公开(公告)日：2009-08-25
申请号：US10655695
申请日：2003-09-05
申请人： Mihail Iotov
发明人： Mihail Iotov
IPC分类号： G06T11/20 , G01R13/02 , G01R31/28 , G06F17/50 , G06F1/12
CPC分类号： G06F17/5031 , G06T11/206
摘要： Techniques for organizing and displaying timing data derived from an EDA tool are provided that allows users to easily extract, analyze, and manipulate portions of the timing data relevant to particular user requirements. Relevant portions of signal waveforms are displayed on an interactive graphical user interface (GUI). Time points on the waveforms are marked with pointers so that users can easily visualize the relationships between different signals. A user can also extract relevant timing data from the EDA tool by manipulating the GUI. Manipulating and understanding circuit design requirements affects all of the design cycle and the quality of the final result from an EDA tool. A user can visualize all aspects of timing analysis on the GUI, such as clock skew, and the setup/hold relationship. A data entry approach is provided that can be used for natural and intuitive manipulation of various timing relationships.
摘要翻译：提供了用于组织和显示从EDA工具导出的定时数据的技术，其允许用户容易地提取，分析和操纵与特定用户需求相关的定时数据的部分。信号波形的相关部分显示在交互式图形用户界面（GUI）上。波形上的时间点用指针标记，以便用户可以轻松地显示不同信号之间的关系。用户还可以通过操纵GUI从EDA工具提取相关的定时数据。操作和理解电路设计要求影响EDA工具的最终结果的所有设计周期和质量。用户可以在GUI上显示时序分析的所有方面，例如时钟偏移以及建立/保持关系。提供了可以用于各种时序关系的自然和直观操纵的数据输入方法。

10. 发明申请

US20070261014A1 System and method for design entry and synthesis in programmable logic devices 有权
公开(公告)号：US20070261014A1
公开(公告)日：2007-11-08
申请号：US11592734
申请日：2006-11-03
申请人： Mihail Iotov , Greg Starr
发明人： Mihail Iotov , Greg Starr
IPC分类号： G06F17/50
CPC分类号： H03K19/17732 , G11C27/00 , H03L7/0891 , H03L7/093 , H03L7/183
摘要： A system and method facilitates the implementation of analog circuitry in electronic programmable devices. A user can specify user measurable parameters for analog features of the circuit, without requiring knowledge of the internal way in which those analog circuit are implemented in the programmable device to achieve desired properties of the analog parameters of interest. The implementation can be performed in different devices which may implement the analog circuit in vastly different ways.

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