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    • 1. 发明申请
      US20090161738A1 Transceiver system with reduced latency uncertainty 有权
    • Transceiver system with reduced latency uncertainty
    • 收发器系统具有降低的延迟不确定性
    • US20090161738A1
    • 2009-06-25
    • US12283652
    • 2008-09-15
    • Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
    • Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
    • H04L7/00 , H04B1/38
    • H04L25/14
    • A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
    • 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US09559881B2 Transceiver system with reduced latency uncertainty 有权
    • Transceiver system with reduced latency uncertainty
    • 收发器系统具有降低的延迟不确定性
    • US09559881B2
    • 2017-01-31
    • US12283652
    • 2008-09-15
    • Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
    • Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
    • H04L7/00 , H04B1/38 , H04L25/14
    • H04L25/14
    • A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
    • 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5157656A Nyblet time switch 失效
    • Nyblet time switch
    • NYBLET时间开关
    • US5157656A
    • 1992-10-20
    • US559956
    • 1990-07-31
    • Andy Turudic , Mark G. Schnell
    • Andy Turudic , Mark G. Schnell
    • H04J3/04 , H04J3/00 , H04J3/16 , H04M11/00 , H04Q11/04
    • H04J3/1647 , H04Q11/0428 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/13367
    • A data transmission method and apparatus provides for transmitting lower data rate information in a higher data transmission rate environment. Information entities to be transmitted are broken into smaller entitles called nyblets. Higher data transmission rates are accomodated by accelerating a clock and clocking nyblets from memory at rate that allows the nyblets to be serially assembled into expected bit length words. Lower data rate information, which in conventional systems was transmitted redundantly to achieve compatibility with higher data rate systems, is now transmitted without duplication as a plurality of nyblets in series until the expected bit length is achieved. The result is that more information can be transmitted over a communication medium, since duplicate or redundant transmission of lower data rate information is avoided.
    • 数据传输方法和装置提供在较高数据传输速率环境中传输较低数据速率信息。 要发送的信息实体被分解成较小的权利称为冒号。 更高的数据传输速率是通过以速率加速时钟和时钟从存储器的速度来容纳高速数据传输速率的，允许将指示符串连接到预期位长度字中。 在传统系统中冗余传输以实现与较高数据速率系统的兼容性的较低数据速率信息现在被传输而不重复，作为串联的多个低音符号，直到达到期望的比特长度。 结果是可以通过通信介质传输更多的信息，因为避免了较低数据速率信息的重复或冗余传输。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US06310509B1 Differential multiplexer with high bandwidth and reduced crosstalk 失效
    • Differential multiplexer with high bandwidth and reduced crosstalk
    • 具有高带宽和减少串扰的差分多路复用器
    • US06310509B1
    • 2001-10-30
    • US09208625
    • 1998-12-08
    • William H. Davenport , Andy Turudic
    • William H. Davenport , Andy Turudic
    • H03K1762
    • H04J3/047 , H03K17/162 , H03K17/6264 , H03K17/693
    • A multiplexer includes a first input device that receives a first input signal and a first select signal. When the first select signal has a first state, the first input device generates a first voltage at a first node in response to the first input signal. When the first select signal has a second state, the first input device generates a first reference voltage at the first node. A second input device receives a second input signal and a second select signal related to the first select signal. When the second select signal has a first state, the second input device generates a second voltage at a second node in response to the second input signal. When the second select signal has a second state, the second input device generates a second reference voltage at the second node. A first output buffer has an input terminal coupled to the first node and an output terminal coupled to an output node. The first output buffer tracks the first voltage at the output terminal, and presents a high impedance at the output terminal when the first reference voltage is present at the first node. A second output buffer has an input terminal coupled to the second node and an output terminal coupled to the output node. The second output buffer tracks the second voltage at the output terminal, and presents a high impedance at the output terminal when the second reference voltage is present at the second node.
    • 多路复用器包括接收第一输入信号和第一选择信号的第一输入装置。 当第一选择信号具有第一状态时，第一输入装置响应于第一输入信号在第一节点产生第一电压。 当第一选择信号具有第二状态时，第一输入装置在第一节点产生第一参考电压。 第二输入装置接收与第一选择信号相关的第二输入信号和第二选择信号。 当第二选择信号具有第一状态时，第二输入装置响应于第二输入信号在第二节点产生第二电压。 当第二选择信号具有第二状态时，第二输入装置在第二节点产生第二参考电压。 第一输出缓冲器具有耦合到第一节点的输入端和耦合到输出节点的输出端。 第一输出缓冲器跟踪输出端处的第一电压，并且当第一参考电压存在于第一节点时，在输出端呈现高阻抗。 第二输出缓冲器具有耦合到第二节点的输入端和耦合到输出节点的输出端。 第二输出缓冲器在输出端跟踪第二电压，并且当第二参考电压存在于第二节点时，在输出端呈现高阻抗。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5452306A Out-of-band embedded overhead architecture for a transmission network 失效
    • Out-of-band embedded overhead architecture for a transmission network
    • 用于传输网络的带外嵌入式架构
    • US5452306A
    • 1995-09-19
    • US117936
    • 1993-09-07
    • Andy Turudic , Samuel Sigarto
    • Andy Turudic , Samuel Sigarto
    • H04J3/12 , H04J3/16
    • H04J3/1611 , H04J3/12 , H04J3/1635
    • An interface is disclosed that formats a first link (a source link--e.g., a T1 link) having N channels to fit into a second link (a source link--e.g., a PCM-30 or a doubled T1 link) having N+M channels. Each of the first and second links are implemented with primary rate carrier links, and have a standard payload portion and a standard overhead portion. A mechanism is disclosed for routing information between the first link and the second link, so that information being transported over the first link can also be transported over the second link. An adding mechanism is also disclosed for routing supplemental overhead information to at least one added overhead channel within the second link, wherein the added overhead channel occupies a standard payload portion of the second link. An overhead information bit is disclosed, which transmits information within a (k)th bit of an (l)th channel of each frame of the second link. An information bit signal is formed with at least five consecutive of the (k)th bits. Using the formed information bit signal, information is conveyed regarding the communications link. A path overhead byte is provided for transportation within the added overhead channel of the second link, and includes various overhead bits, including, e.g., the information bit noted above, for performing several maintenance and performance monitoring functions. Four of the bits within the path overhead byte are essentially equivalent to bits within an overhead byte provided for SONET networks.
    • 公开了一种接口，其格式化具有N个信道的第一链路（源链路（例如，T1链路））以适合具有N + M的第二链路（源链路 - 例如PCM-30或双T1连接） 频道 第一和第二链路中的每一个由主速率载波链路实现，并且具有标准有效载荷部分和标准开销部分。 公开了用于在第一链路和第二链路之间路由信息的机制，使得通过第一链路传输的信息也可以在第二链路上传输。 还公开了一种添加机制，用于将补充开销信息路由到第二链路内的至少一个附加开销信道，其中，所附加的开销信道占用第二链路的标准有效载荷部分。 公开了一种开销信息比特，其在第二链路的每个帧的第（1）个信道的第（k）比特内发送信息。 信息位信号由（k）位的至少五个连续形成。 使用形成的信息位信号，关于通信链路传送信息。 路径开销字节被提供用于在第二链路的附加开销信道内的传输，并且包括各种开销比特，包括例如上述的信息比特，用于执行若干维护和性能监视功能。 路径开销字节中的四个位基本上等同于为SONET网络提供的开销字节内的位。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US08098787B1 Method and apparatus for precision quantization of temporal spacing between two events 有权
    • Method and apparatus for precision quantization of temporal spacing between two events
    • 用于两次事件之间的时间间隔的精确量化的方法和装置
    • US08098787B1
    • 2012-01-17
    • US11956260
    • 2007-12-13
    • Andy Turudic
    • Andy Turudic
    • H03D3/24
    • H04L25/14 , H03M9/00 , H04L7/0337 , H04L25/069
    • One or two Serializer/Deserializer (SerDes) modules are used to measure the time between two pulses with high resolution. A PLL inside a SerDes block is locked to a reference clock and an input signal is passed through a storage element to create a serial data stream that is converted into a parallel data stream by a demultiplexer inside the SerDes. The parallel data is stored in a bit logic unit that compares the parallel data to a second parallel data obtained in similar fashion in another SerDes from a second input signal. The time between the two pulses is then calculated as the number of cycles in the serial data stream that corresponds to the number of bits between the positions of the two events.
    • 一个或两个串行器/解串器（SerDes）模块用于测量高分辨率的两个脉冲之间的时间。 SerDes块内的PLL被锁定到参考时钟，并且输入信号通过存储元件，以创建由SerDes内部的解复用器转换成并行数据流的串行数据流。 并行数据存储在比特逻辑单元中，该比特逻辑单元将并行数据与从第二输入信号的另一个SerD中以类似方式获得的第二并行数据进行比较。 然后将两个脉冲之间的时间计算为串行数据流中与两个事件的位置之间的位数相对应的周期数。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06359948B1 Phase-locked loop circuit with reduced jitter 失效
    • Phase-locked loop circuit with reduced jitter
    • 减少抖动的锁相环电路
    • US06359948B1
    • 2002-03-19
    • US09251703
    • 1999-02-17
    • Andy Turudic , David E. McNeill
    • Andy Turudic , David E. McNeill
    • H03D324
    • H03K23/66 , H03L7/183
    • An improved phase-locked loop circuit includes a variable-frequency oscillator that generates a first oscillator signal, a reference signal source that generates a second oscillator signal, a control block that generates a select signal, and a frequency divider that receives as an input signal one of the first and second oscillator signals. The frequency divider also receives the select signal from the control block. The frequency divider generates a plurality of frequency-divided signals in response to the input signal, and passes through a selected one of the plurality of frequency-divided signals as an output signal in response to the select signal. The frequency divider also synchronizes its output signal to its input signal. The phase-locked loop also includes a frequency comparator that receives the output signal of the frequency divider and a signal derived from one of the first and second oscillator signals. The frequency comparator compares the output signal of the frequency divider to the signal derived from one of the first and second oscillator signals, and provides a feedback signal to the variable-frequency oscillator reflecting this comparison. In this phase-locked loop circuit, the number of signal regenerators introduced by the programmable frequency divider is effectively limited to one, thereby reducing the jitter introduced by the frequency divider.
    • 改进的锁相环电路包括产生第一振荡器信号的可变频率振荡器，产生第二振荡器信号的参考信号源，产生选择信号的控制块，以及接收作为输入信号的分频器 第一和第二振荡器信号之一。 分频器还从控制块接收选择信号。 分频器响应于输入信号产生多个分频信号，并且响应于选择信号而通过多个分频信号中的所选择的一个作为输出信号。 分频器还将其输出信号与其输入信号同步。 锁相环还包括频率比较器，其接收分频器的输出信号和从第一和第二振荡器信号之一导出的信号。 频率比较器将分频器的输出信号与从第一和第二振荡器信号中的一个导出的信号进行比较，并且向可变频率振荡器提供反馈该比较的反馈信号。 在该锁相环电路中，由可编程分频器引入的信号再生器的数量被有效地限制在一个，从而降低了由分频器引入的抖动。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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