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1. 发明申请

US20120023281A1 Single-chip microcomputer 审中-公开
标题翻译：单片机
公开(公告)号：US20120023281A1
公开(公告)日：2012-01-26
申请号：US13065588
申请日：2011-03-24
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F13/36 , G11C11/34
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

2. 发明申请

US20080313444A1 MICROCOMPUTER AND DIVIDING CIRCUIT 审中-公开
标题翻译：微型计算机和分流电路
公开(公告)号：US20080313444A1
公开(公告)日：2008-12-18
申请号：US12195856
申请日：2008-08-21
申请人： Shumpei KAWASAKI , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei KAWASAKI , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F9/06
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
摘要翻译：这里公开了采用通用寄存器方法的微计算机MCU。微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。并且，通过注意码位来执行编码除法的控制。

3. 发明授权

US07371687B2 Electronic circuit device 失效
标题翻译：电子电路装置
公开(公告)号：US07371687B2
公开(公告)日：2008-05-13
申请号：US11475961
申请日：2006-06-28
申请人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
发明人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
IPC分类号： H01L23/52
CPC分类号： G06F11/261 , G06F11/267 , G06F15/7867 , H01L25/18 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.
摘要翻译：电子电路装置具有高密度安装板（2），微型计算机（3）和随机存取存储器（7）设置在其上，通过用于高速数据的专用存储器总线（12）彼此连接传输，由FPGA表示的可变逻辑电路的可编程器件（8）和可存储微型计算机的操作程序的电可重写非易失性存储器（16）。高密度安装板在底面上具有外部安装销，使其可以以与系统片上多芯片模块相同的方式安装在母板上。通过在可编程器件上设置预期的逻辑功能，可以模拟由电子电路器件实现的基于硬件的功能。通过将操作程序写入非易失性存储器，可以模拟要实现的基于软件的功能。因此，该设备便于系统开发初期的调试，配置原型系统，有助于整个系统开发，原型制作和大规模生产的时间缩短。

4. 发明申请

US20060244122A1 Electronic circuit device 失效
标题翻译：电子电路装置
公开(公告)号：US20060244122A1
公开(公告)日：2006-11-02
申请号：US11475936
申请日：2006-06-28
申请人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
发明人： Ryo Fujita , Osamu Kubo , Kouki Noguchi , Masaharu Kubo , Michihiro Mishima , Yasuhiko Takahashi
IPC分类号： H01L23/52
CPC分类号： G06F11/261 , G06F11/267 , G06F15/7867 , H01L25/18 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.
摘要翻译：电子电路装置具有高密度安装板（2），微型计算机（3）和随机存取存储器（7）设置在其上，通过用于高速数据的专用存储器总线（12）彼此连接传输，由FPGA表示的可变逻辑电路的可编程器件（8）和可存储微型计算机的操作程序的电可重写非易失性存储器（16）。高密度安装板在底面上具有外部安装销，使其可以以与系统片上多芯片模块相同的方式安装在母板上。通过在可编程器件上设置预期的逻辑功能，可以模拟由电子电路器件实现的基于硬件的功能。通过将操作程序写入非易失性存储器，可以模拟要实现的基于软件的功能。因此，该设备便于系统开发初期的调试，配置原型系统，有助于整个系统开发，原型制作和大规模生产的时间缩短。

5. 发明授权

US06591294B2 Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals 失效
标题翻译：具有微型计算机的处理系统，每个微型计算机可在主模式和从属模式下使用可配置的总线访问控制终端和总线使用优
公开(公告)号：US06591294B2
公开(公告)日：2003-07-08
申请号：US09918625
申请日：2001-07-30
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1516
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

6. 发明授权

US5966407A Bus driving system and integrated circuit device using the same 失效
标题翻译：总线驱动系统和集成电路装置使用相同
公开(公告)号：US5966407A
公开(公告)日：1999-10-12
申请号：US251185
申请日：1994-05-31
申请人： Mitsuru Hiraki , Hirotsugu Kojima , Masaru Kokubo , Takafumi Kikuchi , Yuji Hatano , Kouki Noguchi , Masao Hotta
发明人： Mitsuru Hiraki , Hirotsugu Kojima , Masaru Kokubo , Takafumi Kikuchi , Yuji Hatano , Kouki Noguchi , Masao Hotta
IPC分类号： G06F13/40 , H04B3/00 , H04B25/00
CPC分类号： G06F13/4077 , Y02B60/1228 , Y02B60/1235
摘要： A bus driving system includes n bus wires having data signal wires and control signal wires, (n-1) switching circuits constituting driver circuits at a transmitting end, a precharge circuitry for precharging (n-2) bus wires and (n-1)-th bus wire with a control circuit for redistributing wire capacitances of transmission lines formed by the bus wires, and a predischarge circuitry for predischarging n-th bus wire. The switching circuits control conduction and non-conduction between (n-2) bus wires, (n-1)-th bus wire and n-th bus wire, wherein the (n-2) switching circuits respond to (n-2) bit signals and a control signal, while the (n-1)-th switching circuit responds to the control signal. The signal from the transmitting end is detected by a detection circuit at a receiving end via the transmission lines.
摘要翻译：一种总线驱动系统，包括具有数据信号线和控制信号线的n条母线，在发送端构成驱动电路的（n-1）个开关电路，用于预充电（n-2）母线的预充电电路和（n-1）具有用于重新分配由总线构成的传输线的线电容的控制电路的总线，以及用于对第n总线进行预充电的预放电电路。开关电路控制（n-2）总线，（n-1）总线和第n总线之间的导通和非导通，其中（n-2）个开关电路响应于（n-2）位置信号和控制信号，而第（n-1）个开关电路响应于控制信号。来自发送端的信号由接收端的检测电路经由传输线检测。

7. 发明授权

US5832248A Semiconductor integrated circuit having CPU and multiplier 失效
标题翻译：具有CPU和乘法器的半导体集成电路
公开(公告)号：US5832248A
公开(公告)日：1998-11-03
申请号：US555262
申请日：1995-11-08
申请人： Kazumasa Kishi , Shigeki Masumura , Hideo Nakamura , Kouki Noguchi , Shumpei Kawasaki , Yasushi Akao
发明人： Kazumasa Kishi , Shigeki Masumura , Hideo Nakamura , Kouki Noguchi , Shumpei Kawasaki , Yasushi Akao
IPC分类号： G06F7/52 , G06F7/506 , G06F7/523 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/78 , G06F12/00
CPC分类号： G06F9/3001 , G06F15/7864 , G06F9/325 , G06F9/3885
摘要： A logic LSI chip includes a CPU, a bus, a memory, and a multiplier. In addition, the logic LSI chip includes a command signal line for transferring, from the CPU to the multiplier, a command regarding a multiplication instruction relating to data read out, while the data is being read out from the memory, so that the multiplier can fetch the data directly from the bus. While the CPU is reading data from the memory, therefore, a command of a multiplication instruction relating to data read out is transferred from the CPU to the multiplier. A bus cycle control circuit receives a state signal from the multiplier when the multiplier is executing a repetitional operation and the bus cycle control circuit responds to the state signal by signalling the CPU to delay issuance of a succeeding command to the multiplier.
摘要翻译：逻辑LSI芯片包括CPU，总线，存储器和乘法器。此外，逻辑LSI芯片包括用于在从存储器读出数据的同时从CPU向乘法器传送关于与读出的数据相关的乘法指令的命令的命令信号线，使得乘法器从总线直接获取数据。因此，当CPU从存储器读取数据时，与读出的数据相关的乘法指令的命令从CPU传送到乘法器。当乘法器执行重复操作时，总线周期控制电路接收来自乘法器的状态信号，并且总线周期控制电路通过发信号通知CPU来延迟向乘法器发出后续命令来响应状态信号。

8. 发明授权

US5452451A System for plural-string search with a parallel collation of a first partition of each string followed by finite automata matching of second partitions 失效
标题翻译：用于多字符串搜索的系统，其中每个字符串的第一分区的并行排序以及第二分区的有限自动机匹配
公开(公告)号：US5452451A
公开(公告)日：1995-09-19
申请号：US349124
申请日：1994-12-01
申请人： Mitsuru Akizawa , Hisamitsu Kawaguchi , Kanji Kato , Atsushi Hatakeyama , Kouki Noguchi , Hiromichi Fujisawa
发明人： Mitsuru Akizawa , Hisamitsu Kawaguchi , Kanji Kato , Atsushi Hatakeyama , Kouki Noguchi , Hiromichi Fujisawa
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , Y10S707/99936 , Y10S707/99937
摘要： A parallel comparator for performing a parallel and high-speed processing for collation of partial character strings which are partially taken out of a plurality of character strings of interest to be searched out with a character string to be searched in which document data to be searched is arranged sequentially from a leading character, is provided in a front stage of an automaton executing device. Only when a part of the character string to be searched coincides with the partial character string set in the comparator, the collation of the remaining portion of the character string to be searched is performed by the automaton executing device. Also, it is possible to set "don't care" in which a character at any position in the partial character string is ignored at the time of comparison by the comparator and to set a negation condition in which the comparison by the comparator is made taking the negation of a character at any position in the partial character string.
摘要翻译：一种并行比较器，用于执行并行和高速处理，用于将要搜索的多个感兴趣的字符串部分地从要搜索的文档数据中搜索的字符串中部分取出的部分字符串对准，设置在自动机执行装置的前级中，从主角排列顺序排列。只有当要搜索的字符串的一部分与比较器中设置的部分字符串一致时，由自动机执行装置执行要搜索的字符串的剩余部分的核对。此外，可以设置在比较器比较时忽略部分字符串中的任何位置的字符的“无关心”，并且设置比较器进行比较的否定条件在部分字符串中的任何位置取一个字符。

9. 发明授权

US5321845A Single-chip microcomputer including non-volatile memory elements 失效
标题翻译：单片机包括非易失性存储元件
公开(公告)号：US5321845A
公开(公告)日：1994-06-14
申请号：US94920
申请日：1993-07-22
申请人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
发明人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F15/78 , G06F9/06
CPC分类号： G06F9/24 , G06F15/7814
摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.
摘要翻译：内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

10. 发明授权

US5307266A Information processing system and method for processing document by using structured keywords 失效
标题翻译：信息处理系统和使用结构化关键词处理文档的方法
公开(公告)号：US5307266A
公开(公告)日：1994-04-26
申请号：US741760
申请日：1991-08-07
申请人： Takehisa Hayashi , Kouki Noguchi , Tsuneya Kurihara , Masahiro Abe
发明人： Takehisa Hayashi , Kouki Noguchi , Tsuneya Kurihara , Masahiro Abe
IPC分类号： G06F17/30 , G06F15/40
CPC分类号： G06F17/30011
摘要： A document processing system for processing documents by using structured keywords comprises an output system and a receiver system. The output system includes a first storage for storing a structured keyword dictionary containing structured keywords among which relations are systematically structured, and linkage unit providing linkage information for establishing correspondences between constituent parts of an input document and corresponding ones of the keywords. The receiver system is coupled to the output system and includes a second storage for storing structured keywords among which relations are systematically structured, and retrieving unit having inputs supplied with the document and the linkage information for retrieving the document to thereby form data of a predetermined edition format by using the structured keyword read out from the second storage. Data transfer between the output system and the receiver systems can be performed either on-line or off-line.
摘要翻译：通过使用结构化关键词处理文档的文档处理系统包括输出系统和接收器系统。输出系统包括：第一存储器，用于存储包含结构化关键字的结构化关键字字典，其中系统地构造关系;以及链接单元，提供用于建立输入文档的组成部分与对应关键字之间的对应关系的链接信息。接收机系统耦合到输出系统，并且包括用于存储结构化关键字的第二存储器，其中系统地构造关系，以及具有提供有文档的输入的检索单元和用于检索文档的链接信息，从而形成预定版本的数据通过使用从第二个存储器读出的结构化关键字的格式。输出系统和接收机系统之间的数据传输可以在线还是离线进行。

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