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1. 发明授权

US5966407A Bus driving system and integrated circuit device using the same 失效
标题翻译：总线驱动系统和集成电路装置使用相同
公开(公告)号：US5966407A
公开(公告)日：1999-10-12
申请号：US251185
申请日：1994-05-31
申请人： Mitsuru Hiraki , Hirotsugu Kojima , Masaru Kokubo , Takafumi Kikuchi , Yuji Hatano , Kouki Noguchi , Masao Hotta
发明人： Mitsuru Hiraki , Hirotsugu Kojima , Masaru Kokubo , Takafumi Kikuchi , Yuji Hatano , Kouki Noguchi , Masao Hotta
IPC分类号： G06F13/40 , H04B3/00 , H04B25/00
CPC分类号： G06F13/4077 , Y02B60/1228 , Y02B60/1235
摘要： A bus driving system includes n bus wires having data signal wires and control signal wires, (n-1) switching circuits constituting driver circuits at a transmitting end, a precharge circuitry for precharging (n-2) bus wires and (n-1)-th bus wire with a control circuit for redistributing wire capacitances of transmission lines formed by the bus wires, and a predischarge circuitry for predischarging n-th bus wire. The switching circuits control conduction and non-conduction between (n-2) bus wires, (n-1)-th bus wire and n-th bus wire, wherein the (n-2) switching circuits respond to (n-2) bit signals and a control signal, while the (n-1)-th switching circuit responds to the control signal. The signal from the transmitting end is detected by a detection circuit at a receiving end via the transmission lines.
摘要翻译：一种总线驱动系统，包括具有数据信号线和控制信号线的n条母线，在发送端构成驱动电路的（n-1）个开关电路，用于预充电（n-2）母线的预充电电路和（n-1）具有用于重新分配由总线构成的传输线的线电容的控制电路的总线，以及用于对第n总线进行预充电的预放电电路。开关电路控制（n-2）总线，（n-1）总线和第n总线之间的导通和非导通，其中（n-2）个开关电路响应于（n-2）位置信号和控制信号，而第（n-1）个开关电路响应于控制信号。来自发送端的信号由接收端的检测电路经由传输线检测。

2. 发明申请

US20060174052A1 Integrated circuit and information processing device 审中-公开
标题翻译：集成电路和信息处理装置
公开(公告)号：US20060174052A1
公开(公告)日：2006-08-03
申请号：US11047670
申请日：2005-02-02
申请人： Nobukazu Kondo , Kei Suzuki , Kouki Noguchi , Itaru Nonomura
发明人： Nobukazu Kondo , Kei Suzuki , Kouki Noguchi , Itaru Nonomura
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provided on a transfer path in an on-chip bus on the LSI for temporarily storing transfer data. With this transferring buffer, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to the transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave, thereby improving the processing performance of the entire system.
摘要翻译：在使用片上总线的LSI系统中，当总线上的传输由于目的地模块中的满载缓冲器而被延迟时，源模块不能进行下一个处理。通过在LSI上的片上总线的传送路径上提供的用于临时存储传送数据的传送缓冲器来消除这种不希望的情况。使用此传输缓冲区，即使指定为目标的从模块中的缓冲区已完全加载，也不能接受任何更多传输，总线主机可将数据传输到片上总线上提供的传输缓冲区。因此，无论总线主机中的缓冲器的状态如何，总线主机不会等待执行转移，从而提高整个系统的处理性能。

3. 发明授权

US06343357B1 Microcomputer and dividing circuit 失效
标题翻译：微电脑和分频电路
公开(公告)号：US06343357B1
公开(公告)日：2002-01-29
申请号：US09632332
申请日：2000-08-03
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F1500
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
摘要翻译：采用通用寄存器方法的微型计算机MCU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。并且，通过注意代码位来执行编码除法的控制。

4. 发明授权

US06279063B1 Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller 有权
标题翻译：具有至少第一和第二微型计算机的微机系统，每个微型计算机均可在主模式和从属模式下操作，具有可配置的总线访问控制终端和总线使用优先级控制器
公开(公告)号：US06279063B1
公开(公告)日：2001-08-21
申请号：US09467087
申请日：1999-12-10
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1300
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

5. 发明授权

US06223265B1 Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal 有权
标题翻译：单片机同步控制外部同步存储器，响应存储器时钟信号和时钟使能信号
公开(公告)号：US06223265B1
公开(公告)日：2001-04-24
申请号：US09192093
申请日：1998-11-13
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1200
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

6. 发明授权

US06212620B1 Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals 有权
标题翻译：单片机可在主从模式下工作，并具有可配置的总线控制端子
公开(公告)号：US06212620B1
公开(公告)日：2001-04-03
申请号：US09191313
申请日：1998-11-13
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1500
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

7. 发明授权

US5991545A Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word 失效
标题翻译：微型计算机具有用于位移的可变位宽度区域和用于处理大于指令字的立即数据的电路
公开(公告)号：US5991545A
公开(公告)日：1999-11-23
申请号：US478730
申请日：1995-06-07
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/22
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
摘要翻译：这里公开了采用通用寄存器方法的微计算机MCU。微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。并且，通过注意码位来执行编码除法的控制。

8. 发明授权

US5530965A Multiply connectable microprocessor and microprocessor system 失效
标题翻译：可连接的微处理器和微处理器系统
公开(公告)号：US5530965A
公开(公告)日：1996-06-25
申请号：US517151
申请日：1995-08-21
申请人： Shumpei Kawasaki , Kaoru Fukada , Mitsuru Watabe , Kouki Noguchi , Kiyoshi Matsubara , Isamu Mochizuki , Kazufumi Suzukawa , Shigeki Masumura , Yasushi Akao , Eiji Sakakibara
发明人： Shumpei Kawasaki , Kaoru Fukada , Mitsuru Watabe , Kouki Noguchi , Kiyoshi Matsubara , Isamu Mochizuki , Kazufumi Suzukawa , Shigeki Masumura , Yasushi Akao , Eiji Sakakibara
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78 , G06F13/00
CPC分类号： G06F15/7832 , G06F13/4239 , G06F15/786
摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.
摘要翻译：一种易于使用和直接连接到动态和静态RAM以及其他外围电路等存储器的微型计算机。微型计算机具有选通信号输出端子CASH *，CASL *和RAS *，用于直接连接到动态RAM，以及芯片选择信号输出端子CS0 *至CS6 *，用于与选通信号输出的输出并行输出芯片选择信号终端。微型计算机还包括用于根据需要输出未复用或多路复用的地址信号的地址输出端子和用于选择性地输出地址信号以符合多总线接口方案的数据I / O端子。

9. 发明授权

US5428808A Single-chip microcomputer 失效
标题翻译：单片机
公开(公告)号：US5428808A
公开(公告)日：1995-06-27
申请号：US217826
申请日：1994-03-25
申请人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
发明人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F15/78 , G06F9/06
CPC分类号： G06F9/24 , G06F15/7814
摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.
摘要翻译：内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

10. 发明授权

US5398206A Semiconductor memory device with data error compensation 失效
标题翻译：具有数据误差补偿的半导体存储器件
公开(公告)号：US5398206A
公开(公告)日：1995-03-14
申请号：US654379
申请日：1991-02-12
申请人： Mitsuru Akizawa , Kazuhiko Iwasaki , Kouki Noguchi , Ryuuji Shibata , Noboru Yamaguchi
发明人： Mitsuru Akizawa , Kazuhiko Iwasaki , Kouki Noguchi , Ryuuji Shibata , Noboru Yamaguchi
IPC分类号： G11C29/00 , G11C29/24 , G11C7/00 , G11C8/00
CPC分类号： G11C29/808 , G11C29/24 , G11C29/74 , G11C29/76
摘要： A semiconductor memory device includes signal lines, a decoder for decoding an inputted address to output the decoded result to some of the signal lines, a matrixed memory array, a part of which being pre-specified as a compensated area, read out means for reading out data from memory cells in an area specified in accordance with a decode signal on the some signal line, a detector for detecting that the address is related with the compensated area from the decode signal on the some signal lines, the compensated area being pre-related with the some signal lines, and a fixed data outputting circuit for merging predetermined data into a predetermined part of the data read out from the memory cells in accordance with the detection signal to output the merged data. The fixed data outputting circuit is controlled by a control circuit in response to a merge control signal to output the data read out from the memory cells without the merging operation.
摘要翻译：半导体存储器件包括信号线，用于对输入的地址进行解码以将解码结果输出到某些信号线的解码器，其一部分被预先指定为补偿区域的矩阵存储器阵列，读出装置在某些信号线上根据解码信号指定的区域中的存储器单元输出数据;检测器，用于检测所述地址与所述一些信号线上的解码信号中的所述补偿区域相关，所述补偿区域是预处理的，与一些信号线相关联的固定数据输出电路，以及用于根据检测信号将预定数据合并到从存储器单元读出的数据的预定部分中以输出合并数据的固定数据输出电路。固定数据输出电路由控制电路根据合并控制信号进行控制，以输出从存储单元读出的数据，而不进行合并操作。

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