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1. 发明申请

US20110050958A1 IMAGE PICKUP DEVICE, IMAGE PICKUP METHOD, AND INTEGRATED CIRCUIT 有权
标题翻译：图像拾取器件，图像拾取方法和集成电路
公开(公告)号：US20110050958A1
公开(公告)日：2011-03-03
申请号：US12669861
申请日：2009-04-10
申请人： Koji Kai
发明人： Koji Kai
IPC分类号： H04N5/76 , H04N5/228
CPC分类号： H04N5/772 , G11B27/034 , H04N5/765 , H04N5/775 , H04N5/907
摘要： The moving picture image pickup device includes an image pickup section for obtaining a picked-up moving picture, and an image processing section for processing, per frame, the picked-up moving picture and creating a storage moving picture. The image processing section designates, upon a user's instruction, object images in the picked-up moving picture; sets object trimming images for clipping, out of the picked-up moving picture, the object images, respectively; follows the object images and moving, per frame, the object trimming images in accordance with the object images; sets, per frame, the object trimming images as a first trimming image; sets one image enclosing the object trimming images as a second trimming image; calculates and compares the data sizes of the first and the second trimming images; and selects, as the storage moving picture, an image having a smaller data size, from the first trimming image or the second trimming image.
摘要翻译：运动图像摄取装置包括用于获取拍摄的运动图像的图像拾取部分和用于每帧处理所拾取的运动图像并创建存储运动图像的图像处理部分。图像处理部根据用户的指示指定拍摄的动态图像中的对象图像; 设置用于剪切的对象修剪图像，分别从拾取的运动图像中去除对象图像; 跟踪对象图像并根据对象图像移动每帧对象修剪图像; 将每帧的对象修剪图像设置为第一修剪图像; 将包围对象修整图像的一个图像设置为第二修剪图像; 计算并比较第一和第二修剪图像的数据大小; 并且从第一微调图像或第二微调图像中选择具有较小数据大小的图像作为存储运动图像。

2. 发明申请

US20080034140A1 Bus Arbitrating Device and Bus Arbitrating Method 审中-公开
标题翻译：总线仲裁设备和总线仲裁方法
公开(公告)号：US20080034140A1
公开(公告)日：2008-02-07
申请号：US11579913
申请日：2005-06-15
申请人： Koji Kai
发明人： Koji Kai
IPC分类号： G06F13/368
CPC分类号： G06F13/364
摘要： A bus arbitrating device (100) arbitrates the data transfer request for a plurality of bus-master (11)-(13) connected to a bus (10), and comprises a bus assignment deciding unit (20) and a measurement control unit (30). The measurement control unit (30) includes a time counter (31), a comparator (32), and a timer register (33). The comparator (32) compares a system operating time measured by the time counter (31), with a time period set in the timer register (33). When the system operating time exceeds the time period, the comparator (32) notifies the bus assignment deciding unit (20) of the fact. The bus assignment deciding unit (20) chooses one from a plurality of bus arbitration algorithms as a new bus arbitration algorithm, and arbitrates the bus. Consequently, the deviation of the right of bus use of each bus master can be avoided.
摘要翻译：总线仲裁装置（100）仲裁连接到总线（10）的多个总线主机（11） - （13）的数据传输请求，并且包括总线分配决定单元（20）和测量控制单元 30）。测量控制单元（30）包括时间计数器（31），比较器（32）和定时器寄存器（33）。比较器（32）将由时间计数器（31）测量的系统工作时间与定时器寄存器（33）中设置的时间段进行比较。当系统工作时间超过时间周期时，比较器（32）通知总线分配决定单元（20）。总线分配决定单元（20）从多个总线仲裁算法中选择一个作为新的总线仲裁算法，并对总线进行仲裁。因此，可以避免每个总线主站的总线使用权的偏差。

3. 发明授权

US09202622B2 Welding transformer and welding transformer assembly and welding apparatus 有权
标题翻译：焊接变压器和焊接变压器总成及焊接设备
公开(公告)号：US09202622B2
公开(公告)日：2015-12-01
申请号：US13813174
申请日：2012-06-29
申请人： Koji Kai , Kazuki Houzan , Akira Nagai , Kazuhiro Suzuki
发明人： Koji Kai , Kazuki Houzan , Akira Nagai , Kazuhiro Suzuki
IPC分类号： B23K11/24 , H01F27/06 , H01F38/08 , B23K11/11 , H01F27/40
CPC分类号： H01F38/085 , B23K11/115 , B23K11/241 , B23K2101/18 , H01F2027/408
摘要： It is possible to control a welding in a high speed and a high precision large electric current, and consumption electric power is also reduced. In the welding transformer, a loop magnetic core 25, a wound primary coil 12, plural positive side coils 14 and plural negative side coils 16 that are alternately sandwiched between respective gaps 12a of the primary coil 12, are comprised. A coil is fixed on the other surface of a contact base member 62. On the other surface of the contact base member 62, a first connection polar board 44 is electrically connected to a positive side electric conductor 30 through the first connection polar board 44. A negative side coil 16 is electrically connected to a negative side electric conductor 32. The connecting part of the positive side coil 14 and the negative side coil 16 is electrically connected to the third connection polar board 48. By sandwiching a thin insulation layer 31, a positive side electric conductor 30, a rectifying device 18 and a first polar board 34 are arranged on one side; A negative side electric conductor 32, a rectifying device 20 and a second polar board 36 are arranged on the other side; and the first polar board 34 and the second polar board 36 are electrically connected to a third polar board 38. It is possible to use by combining plural units and by connecting an output side in parallel in a small size and a large capacity.
摘要翻译：可以高速，高精度的大电流控制焊接，消耗电力也降低。在焊接变压器中，包括交替夹在初级线圈12的相应间隙12a之间的环形磁芯25，绕组初级线圈12，多个正侧线圈14和多个负侧线圈16。线圈固定在接触基底构件62的另一个表面上。在接触基底构件62的另一个表面上，第一连接极板44通过第一连接极板44电连接到正侧电导体30。负极侧线圈16与负极侧导体32电连接。正极侧线圈14与负极侧线圈16的连接部与第3连接极板48电连接。通过夹持薄层绝缘层31，正侧导电体30，整流装置18和第一极板34一侧配置; 负侧导电体32，整流装置20和第二极板36配置在另一侧。并且第一极板34和第二极板36电连接到第三极板38.可以通过组合多个单元并且通过以小尺寸和大容量并联连接输出侧来使用。

4. 发明授权

US08885053B2 Integrated circuit and electric device for avoiding latency time caused by contention 有权
标题翻译：集成电路和电气设备，用于避免争用引起的延迟时间
公开(公告)号：US08885053B2
公开(公告)日：2014-11-11
申请号：US10774374
申请日：2004-02-10
申请人： Koji Kai , Tomonori Kataoka , Masayoshi Toujima
发明人： Koji Kai , Tomonori Kataoka , Masayoshi Toujima
IPC分类号： H04N5/225 , H04N21/426 , G06F13/16
CPC分类号： H04N21/42615 , G06F13/161 , H04N21/426 , H04N21/42692 , Y02D10/14
摘要： An integrated circuit including a shared memory connected to a bus, an audio/multiplex/de-multiplex processor accessing the shared memory via the bus, a video processor performing heavy processes accessing the shared memory via the bus, and a local memory accessed by the video processor without passing through the bus. The integrated circuit avoids a latency time caused by access contention, such that a probability that the integrated circuit can complete processes to be done in real time is increased. Image data is displayed on the display device smoothly without deterioration of quality of display.
摘要翻译：一种集成电路，包括连接到总线的共享存储器，经由总线访问共享存储器的音频/多路复用/解复用处理器，执行经由总线访问共享存储器的重工序的视频处理器，以及由该总线访问的本地存储器视频处理器不经过总线。集成电路避免了由访问争用引起的延迟时间，使得集成电路可以实时完成处理的概率增加。图像数据平滑地显示在显示装置上，而不会降低显示质量。

5. 发明授权

US07260223B2 Data transfer system 有权
标题翻译：数据传输系统
公开(公告)号：US07260223B2
公开(公告)日：2007-08-21
申请号：US10327956
申请日：2002-12-26
申请人： Akihiko Inoue , Koji Kai , Masayoshi Toujima , Takashi Hashimoto
发明人： Akihiko Inoue , Koji Kai , Masayoshi Toujima , Takashi Hashimoto
IPC分类号： H04L9/00
CPC分类号： H04L9/00 , H04L9/0662 , H04L2209/60
摘要： In a data-sending device, a data generation section provides input data itself or a bit-inverted version of the input data as intermediate data and generates an inversion signal that indicates whether or not the intermediate data is the bit-inverted version of the input data. An encrypting section generates scrambled data by inserting the inversion signal in the intermediate data at a bit position. A data-receiving device removes the inversion signal from the scrambled data, and restores the input data based on the inversion signal.
摘要翻译：在数据发送装置中，数据产生部分将输入数据本身或输入数据的位反转版本提供为中间数据，并产生指示中间数据是否是输入的位反转版本的反相信号数据。加密部分通过将中间数据中的反转信号插入位位置来产生加扰数据。数据接收装置从加扰数据中去除反相信号，并根据反相信号恢复输入数据。

6. 发明授权

US06243422B1 Waveform shaping method and equipment 失效
标题翻译：波形整形方法和设备
公开(公告)号：US06243422B1
公开(公告)日：2001-06-05
申请号：US09081031
申请日：1998-05-18
申请人： Yoshio Urabe , Shouichi Koga , Hitoshi Takai , Koji Kai , Hidetoshi Yamasaki
发明人： Yoshio Urabe , Shouichi Koga , Hitoshi Takai , Koji Kai , Hidetoshi Yamasaki
IPC分类号： H04L2700
CPC分类号： H03G3/3089 , H03G3/3047 , H04L25/03859 , H04L27/2067 , H04L27/362
摘要： In the transmitter which carries out burst transmission using information data as a packet, if the status is divided into four modes, namely, burst stop mode, burst rising mode, burst continuous mode, and burst falling mode, a waveform shaping equipment designed to read out shaped waveform data for each mode from outputs of either of the two memory tables, the first memory table which holds waveform data for specific data patterns used in common in burst rising mode and burst falling mode and the second memory table which holds waveform data for all data patterns used in the burst continuous mode, or a waveform shaping equipment comprising the third memory table which holds waveform data corresponding to all the data patterns used in the burst rising mode and the fourth memory table which holds waveform data corresponding to all data patterns used in the burst falling mode and generating shaped waveform data by synthesizing the two outputs of the third and the fourth memory tables at the time of burst continuous mode.
摘要翻译：在使用信息数据作为分组执行突发传输的发送机中，如果状态被分为四种模式，即突发停止模式，突发上升模式，突发连续模式和突发下降模式，设计为读取的波形整形设备从两个存储器表中的任一个的输出中输出每个模式的形状波形数据，第一存储表保存用于突发上升模式和突发下降模式中共同使用的特定数据模式的波形数据，以及第二存储器表，其保存用于在脉冲串连续模式中使用的所有数据模式，或波形整形设备，包括保存与突发上升模式中使用的所有数据模式对应的波形数据的第三存储器表，以及保存对应于所有数据模式的波形数据的第四存储器表用于突发下降模式，并通过在t处合成第三和第四存储器表的两个输出来产生形状波形数据他连续时间连续模式。

7. 发明授权

US06968467B2 Decentralized power management system for integrated circuit using local power management units that generate control signals based on common data 有权
标题翻译：使用基于通用数据生成控制信号的本地电源管理单元的集中电路分散式电源管理系统
公开(公告)号：US06968467B2
公开(公告)日：2005-11-22
申请号：US09983296
申请日：2001-10-23
申请人： Akihiko Inoue , Masao Hamada , Koji Kai
发明人： Akihiko Inoue , Masao Hamada , Koji Kai
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A power management system for an integrated circuit has a signal line, a management data generating unit connected to the signal line, and a plurality of management data using units each connected to the signal line. The management data generating unit outputs, to the signal line, power management data for managing power consumption in each of the management data using units, the power management data corresponding to the state of the management data generating unit. Each of the management data using units reads the power management data for common use from the signal line and controls power consumed by the management data using unit based on the power management data.
摘要翻译：用于集成电路的电源管理系统具有信号线，连接到信号线的管理数据产生单元和使用各自连接到信号线的单元的多个管理数据。管理数据生成单元向信号线输出用于管理每个管理数据中使用单位的功耗的电力管理数据，与管理数据生成单元的状态对应的电力管理数据。每个管理数据使用单元从信号线读取用于共同使用的电源管理数据，并且基于电源管理数据来控制由管理数据使用单元消耗的功率。

8. 发明申请

US20140360994A1 WELDING TRANSFORMER AND WELDING TRANSFORMER ASSEMBLY AND WELDING APPARATUS 有权
标题翻译：焊接变压器和焊接变压器总成和焊接设备
公开(公告)号：US20140360994A1
公开(公告)日：2014-12-11
申请号：US13813174
申请日：2012-06-29
申请人： Koji Kai , Kazuki Houzan , Akira Nagai , Kazuhiro Suzuki
发明人： Koji Kai , Kazuki Houzan , Akira Nagai , Kazuhiro Suzuki
IPC分类号： H01F38/08
CPC分类号： H01F38/085 , B23K11/115 , B23K11/241 , B23K2101/18 , H01F2027/408
摘要： It is possible to control a welding in a high speed and a high precision large electric current, and consumption electric power is also reduced. In the welding transformer, a loop magnetic core 25, a wound primary coil 12, plural positive side coils 14 and plural negative side coils 16 that are alternately sandwiched between respective gaps 12a of the primary coil 12, are comprised. A coil is fixed on the other surface of a contact base member 62. On the other surface of the contact base member 62, a first connection polar board 44 is electrically connected to a positive side electric conductor 30 through the first connection polar board 44. A negative side coil 16 is electrically connected to a negative side electric conductor 32. The connecting part of the positive side coil 14 and the negative side coil 16 is electrically connected to the third connection polar board 48. By sandwiching a thin insulation layer 31, a positive side electric conductor 30, a rectifying device 18 and a first polar board 34 are arranged on one side; A negative side electric conductor 32, a rectifying device 20 and a second polar board 36 are arranged on the other side; and the first polar board 34 and the second polar board 36 are electrically connected to a third polar board 38. It is possible to use by combining plural units and by connecting an output side in parallel in a small size and a large capacity.
摘要翻译：可以高速，高精度的大电流控制焊接，消耗电力也降低。在焊接变压器中，包括交替夹在初级线圈12的相应间隙12a之间的环形磁芯25，绕组初级线圈12，多个正侧线圈14和多个负侧线圈16。线圈固定在接触基底构件62的另一个表面上。在接触基底构件62的另一个表面上，第一连接极板44通过第一连接极板44电连接到正侧电导体30。负极侧线圈16与负极侧导电体32电连接。正极侧线圈14与负极侧线圈16的连接部与第3连接极板48电连接。通过夹持薄层绝缘层31，正侧导电体30，整流装置18和第一极板34一侧配置; 负侧导电体32，整流装置20和第二极板36配置在另一侧。并且第一极板34和第二极板36电连接到第三极板38.可以通过组合多个单元并且通过以小尺寸和大容量并联连接输出侧来使用。

9. 发明申请

US20060161877A1 Device and method for data-processing 审中-公开
标题翻译：用于数据处理的设备和方法
公开(公告)号：US20060161877A1
公开(公告)日：2006-07-20
申请号：US11289442
申请日：2005-11-30
申请人： Mana Hamada , Masayoshi Tojima , Koji Kai , Tsuyoshi Nakamura , Akihiko Inoue
发明人： Mana Hamada , Masayoshi Tojima , Koji Kai , Tsuyoshi Nakamura , Akihiko Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/86
摘要： A total specification is divided into a hardware specification and a software specification. With respect to the hardware specification, a first hardware description is described. With respect to the software specification, an object program is generated, which is converted into a second hardware description. The first and second hardware descriptions are logically synthesized into a net list, which includes a part that fulfills the software specification. Since the object program is converted into the second hardware description, which is logically synthesized, the redundancy of the program can be removed and cost for manufacturing hardware can be reduced.
摘要翻译：总规范分为硬件规格和软件规范。关于硬件规范，描述了第一硬件描述。关于软件规范，生成对象程序，将其转换为第二硬件描述。第一和第二硬件描述在逻辑上合成为一个网络列表，其中包括满足软件规范的部分。由于将对象程序转换成逻辑合成的第二硬件描述，所以可以消除程序的冗余，并且可以降低制造硬件的成本。

10. 发明授权

US06446159B1 Semiconductor circuit and method of controlling the same 有权
公开(公告)号：US06446159B1
公开(公告)日：2002-09-03
申请号：US09242049
申请日：1999-02-08
申请人： Koji Kai , Taku Ohsawa , Kazuaki Murakami
发明人： Koji Kai , Taku Ohsawa , Kazuaki Murakami
IPC分类号： G06F1200
摘要： An object of the invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the frequency of times of refreshing operations to thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the memory access time due to contention between refresh and DRAM access of the logic circuit. To achieve the object, the refreshing is done only for rows storing the data used by the logic portion. Further, arbitrary data for which periods from being written in to being read out are overlapping or close to each other are allocated to the same row of the DRAM so as to be stored thereon, and the row is refreshed only during the period of time that the data stored thereon is live.

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