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    • 3. 发明申请
    • Image Encoding Device, Image Decoding Device, and Integrated Circuit Used Therein
    • 图像编码装置,图像解码装置及其中使用的集成电路
    • US20080049832A1
    • 2008-02-28
    • US11628733
    • 2005-06-07
    • Hidekatsu OzekiMasayasu IguchiTakahiro NishiHiroaki ToidaHiroto TomitaAkihiko InoueTakashi Hashimoto
    • Hidekatsu OzekiMasayasu IguchiTakahiro NishiHiroaki ToidaHiroto TomitaAkihiko InoueTakashi Hashimoto
    • H04B1/66
    • H04N19/42H04N19/122H04N19/60
    • An image decoding device and an image encoding device according to the present invention includes an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing, the arithmetic control unit previously defining an arithmetic procedure in each transform mode for each unit executable in one arithmetic operation in the arithmetic unit in association with the number of arithmetic operations.
    • 根据本发明的图像解码装置和图像编码装置包括:运算单元,用于进行运算处理;算术数据存储单元,用于存储运算单元的算术结果;输入选择单元,用于选择是否读取像素数据, 从压缩图像数据或从存储在算术数据存储单元中的像素数据输入到运算单元,并将读取的像素数据输入到运算单元,以及运算控制单元,用于基于所使用的变换模式和 算术单元中的算术运算的数量,由输入选择单元输入到运算单元的像素数据的目的地以及由运算单元计算的运算处理对象的像素数据的组合 算术单元和乘法器系数,运算控制单元先前定义算术 在算术单元中的一个算术运算中,每个单元的每个变换模式的过程与算术运算的数量相关联。
    • 4. 发明授权
    • Method of designing semiconductor integrated circuit
    • 设计半导体集成电路的方法
    • US06493863B1
    • 2002-12-10
    • US09711151
    • 2000-11-14
    • Masao HamadaTakashi HashimotoShun-ichi KurohmaruKoji Kai
    • Masao HamadaTakashi HashimotoShun-ichi KurohmaruKoji Kai
    • G06F1750
    • G06F17/5045
    • After a program is inputted in the high-level synthesis of system design, blocks each for implementing at least one function and an HW resource connection graph showing a plurality of HW resources and a wiring structure connecting the HW resources are generated. From a database storing the HW resources, data on the size of each of the HW resources is inputted such that the HW resources are provisionally placed and a contribution rate of each of parameters which affect power consumption and the like in each of wires between blocks with respect to all the wires is calculated as a weight of signal lines between blocks. Block generation is performed repeatedly till the weight of signal lines between blocks in each of the wires between blocks becomes a threshold value or less. If the weight of signal lines between blocks becomes the threshold value or less, an HDL is outputted. By performing block generation in consideration of a reduction in power consumption and the like in the high-level synthesis on the high level design, overall design efficiency is increased.
    • 在系统设计的高级合成中输入程序之后,生成用于实现至少一个功能的块和表示多个HW资源的HW资源连接图以及连接HW资源的布线结构。 从存储HW资源的数据库中,输入关于每个HW资源的大小的数据,使得临时放置HW资源,并且在块之间的每个线中影响功耗等的每个参数的贡献率, 相对于所有的线被计算为块之间的信号线的权重。 重复执行块生成,直到块之间的每条线之间的块之间的信号线的权重变为阈值或更小。 如果块之间的信号线的权重变为阈值以下,则输出HDL。 考虑到在高级设计的高级合成中的功耗等的降低来执行块生成,总体设计效率提高。