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1. 发明授权

US06446159B1 Semiconductor circuit and method of controlling the same 有权
公开(公告)号：US06446159B1
公开(公告)日：2002-09-03
申请号：US09242049
申请日：1999-02-08
申请人： Koji Kai , Taku Ohsawa , Kazuaki Murakami
发明人： Koji Kai , Taku Ohsawa , Kazuaki Murakami
IPC分类号： G06F1200
摘要： An object of the invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the frequency of times of refreshing operations to thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the memory access time due to contention between refresh and DRAM access of the logic circuit. To achieve the object, the refreshing is done only for rows storing the data used by the logic portion. Further, arbitrary data for which periods from being written in to being read out are overlapping or close to each other are allocated to the same row of the DRAM so as to be stored thereon, and the row is refreshed only during the period of time that the data stored thereon is live.

2. 发明授权

US06349364B1 Cache memory system with variable block-size mechanism 失效
标题翻译：具有可变块大小机制的缓存存储器系统
公开(公告)号：US06349364B1
公开(公告)日：2002-02-19
申请号：US09270254
申请日：1999-03-15
申请人： Koji Kai , Koji Inoue , Kazuaki Murakami
发明人： Koji Kai , Koji Inoue , Kazuaki Murakami
IPC分类号： G06F1204
CPC分类号： G06F12/0886
摘要： The present invention provides for setting the block-size suitably in each address space in order to deal with the difference of the scope within the spatial locality in the address space, and to suppress the generating of the unnecessary replacing. In a cache memory system according to the present invention, a cache memory is provided for temporarily storing the data stored in a main memory, and a processor accesses the cache memory, the cache memory system comprising: a block-size information storing system for storing the size of the data to be replaced between the cache memory and the main memory in every plural storage spaces of predetermined amount within the cache memory; and a system for replacing the data between the storage space in which the cache miss is occurred within the cache memory and the main memory, when the access of the processor to the storage space within the cache memory produces a cache miss, at the block-size corresponding to the storage space producing the cache miss, among the size stored in the block-size information storing system.
摘要翻译：本发明提供了在每个地址空间中适当地设置块大小，以便处理地址空间中的空间局部中的范围的差异，并且抑制不必要的替换的产生。在根据本发明的高速缓冲存储器系统中，提供了一个用于临时存储存储在主存储器中的数据的高速缓冲存储器，并且处理器访问高速缓存存储器，该高速缓冲存储器系统包括：块大小信息存储系统，用于存储在高速缓冲存储器内的预定量的每个多个存储空间中的高速缓冲存储器和主存储器之间要被替换的数据的大小; 以及用于在处理器到高速缓存存储器内的存储空间的访问产生高速缓存未命中时，替换在高速缓存存储器和主存储器之间发生高速缓存未命中的存储空间之间的数据的系统，与存储在块大小信息存储系统中的大小相对应的产生高速缓存未命中的存储空间的大小。

3. 发明授权

US4860190A Computer system for controlling virtual machines 失效
标题翻译：用于控制虚拟机的计算机系统
公开(公告)号：US4860190A
公开(公告)日：1989-08-22
申请号：US902674
申请日：1986-09-02
申请人： Saburo Kaneda , Kazuaki Murakami
发明人： Saburo Kaneda , Kazuaki Murakami
IPC分类号： G06F9/46 , G06F13/10 , G06F13/24
CPC分类号： G06F13/24 , G06F13/10
摘要： A computer system for controlling virtual machines each given a different identification number. The system comprises mask registers and I/O interruption queues, each provided with the same numbers as the virtual machines, and corresponding to any one of the identification numbers. An interrupt handling in any one of the virtual machines can be carried out directly by using a pair of corresponding mask registers and I/O interruption queues without an interposition of the VM monitor.
摘要翻译：一种用于控制虚拟机的计算机系统，每个都具有不同的识别号码。该系统包括掩码寄存器和I / O中断队列，每个具有与虚拟机相同的号码，并且对应于任何一个标识号。可以通过使用一对相应的掩码寄存器和I / O中断队列直接执行任何一个虚拟机中的中断处理，而无需插入VM监视器。

4. 发明申请

US20060242385A1 Dynamically reconfigurable processor 审中-公开
标题翻译：动态可重构处理器
公开(公告)号：US20060242385A1
公开(公告)日：2006-10-26
申请号：US11267026
申请日：2005-11-04
申请人： Kazuaki Murakami , Makoto Shuto , Lovic Gauthier , Takuma Matsuo , Tetsuya Hasebe , Shuichi Kikuchi
发明人： Kazuaki Murakami , Makoto Shuto , Lovic Gauthier , Takuma Matsuo , Tetsuya Hasebe , Shuichi Kikuchi
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30181 , G06F15/7867 , G06F17/5045
摘要： Disclosed is a technology of generating an instruction set architecture (hereinafter, referred to as ‘ISA’) and a series of logic circuit configuration information of a processor for executing an application program from an application program described in a high-level language. The present invention also relates to a custom LSI development platform technology which can design, develop, and manufacture the application specific custom LSI in a short time by applying the generated ISA and logic circuit configuration information to a dynamic logic circuit reconfigurable processor. Furthermore, disclosed is a dynamically reconfigurable processor, which is reconfigurable using the generated logic circuit configuration information. Associated methods are also disclosed.
摘要翻译：本发明公开了一种从高级语言描述的应用程序中执行应用程序的处理器的生成指令集架构（以下称为“ISA”）的一系列逻辑电路配置信息。本发明还涉及通过将生成的ISA和逻辑电路配置信息应用于动态逻辑电路可重配置处理器，可以在短时间内设计，开发和制造特定于应用的定制LSI的定制LSI开发平台技术。此外，公开了一种动态可重构处理器，其可使用所生成的逻辑电路配置信息进行可重构。还公开了相关方法。

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