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1. 发明申请

US20050170580A1 Double polysilicon bipolar transistor 有权
标题翻译：双晶硅双极晶体管
公开(公告)号：US20050170580A1
公开(公告)日：2005-08-04
申请号：US11057259
申请日：2005-02-12
申请人： Purakh Verma , Shao-fu Chu
发明人： Purakh Verma , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L29/737 , H01L21/8249 , H01L21/8222
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/0821 , H01L29/732 , H01L29/7375
摘要： A bipolar transistor, with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.
摘要翻译：一种双极晶体管，其基底具有集电极区域和基底结构。在基底结构上形成发射极结构，并且在基极结构之上形成外部基极结构，并且在发射极结构旁边和间隔开的集电极区上方形成发射极结构。电介质层沉积在衬底上，并且连接被形成为非本征基极结构，发射极结构和集电极区。

2. 发明申请

US20050086780A1 Method of fabricating circular or angular spiral MIM capacitors 审中-公开
标题翻译：制造圆形或角螺旋MIM电容器的方法
公开(公告)号：US20050086780A1
公开(公告)日：2005-04-28
申请号：US10692029
申请日：2003-10-23
申请人： Kai Shao , Chit Ng , Purakh Verma , Jia Zheng , Sanford Chu
发明人： Kai Shao , Chit Ng , Purakh Verma , Jia Zheng , Sanford Chu
IPC分类号： H01L27/08 , H01G7/00 , H01K3/10
CPC分类号： H01L27/0805 , Y10T29/43 , Y10T29/435 , Y10T29/49165
摘要： A method of forming a capacitor comprising the following steps. A substrate having a lower low-k dielectric layer formed thereover is provided with the lower low-k dielectric layer having a dielectric constant of less than about 3.0. Metal vertical electrode plates are formed within the lower low-k dielectric layer so that the adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween. The lower low-k dielectric layer portions between the adjacent metal vertical electrode plates are replaced with high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.
摘要翻译：一种形成电容器的方法，包括以下步骤。具有形成在其上的下部低k电介质层的衬底设置有介电常数小于约3.0的下部低k电介质层。金属垂直电极板形成在下部低k电介质层内，使得相邻的金属垂直电极板之间具有较低的低k电介质层部分。在相邻的金属垂直电极板之间的较低的低k电介质层部分被具有大于约3.0的介电常数的高k电介质材料沟槽部分代替。

3. 发明申请

US20070134854A1 Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process 有权
标题翻译：用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管
公开(公告)号：US20070134854A1
公开(公告)日：2007-06-14
申请号：US11302479
申请日：2005-12-13
申请人： Shaoqiang Zhang , Purakh Verma , Sanford Chu
发明人： Shaoqiang Zhang , Purakh Verma , Sanford Chu
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/82285 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/7378
摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.
摘要翻译：用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。作为插件模块，与SiGe BiCMOS工艺完全集成。高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。自对准N +基极植入可以减少基极电阻和寄生EB电容。极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

4. 发明申请

US20050124131A1 Method of forming an inductor with continuous metal deposition 审中-公开
标题翻译：形成具有连续金属沉积的电感器的方法
公开(公告)号：US20050124131A1
公开(公告)日：2005-06-09
申请号：US11034932
申请日：2005-01-13
申请人： Chit Hweing , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
发明人： Chit Hweing , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
IPC分类号： H01F17/00 , H01L21/02 , H01L23/522 , H01L21/20 , H01L29/00
CPC分类号： H01L28/10 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.
摘要翻译：描述了在硅衬底上制造RF电感器件的方法。沉积低k或其他电介质材料并图案化以形成电感器下板沟槽。沟槽衬有阻挡膜，如填充有铜的TaN和使用化学机械抛光（CMP）平坦化的多余金属。介电材料的第二层被沉积并图案化以形成通孔/沟槽。通孔/沟槽图案填充有阻挡材料，蚀刻通孔/沟槽之间的电介质膜以形成第二组沟槽。这些沟槽用铜填充并平坦化。电介质膜的第三层被沉积并图案化以形成通孔/沟槽。然后用阻挡材料填充通孔/沟槽，蚀刻通孔/沟槽图案之间的电介质膜以形成第三组沟槽。这些沟槽填充有铜金属，并通过CMP去除多余的金属以形成所述RF电感器。

5. 发明申请

US20050116254A1 Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth 有权
标题翻译：横向异质结双极晶体管和使用选择性外延生长的制造方法
公开(公告)号：US20050116254A1
公开(公告)日：2005-06-02
申请号：US10725670
申请日：2003-12-01
申请人： Purakh Verma , Shao-Fu Chu , Lap Chan , Jia Zheng , Jian Li
发明人： Purakh Verma , Shao-Fu Chu , Lap Chan , Jia Zheng , Jian Li
IPC分类号： H01L21/331 , H01L29/737 , H01L21/338 , H01L21/8222 , H01L29/732 , H01L29/739 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.
摘要翻译：提供了一种用于制造异质结双极晶体管的方法。本征收集器结构形成在衬底上。外部基本结构部分地与本征收集器结构重叠。内部基本结构形成在本征收集器结构附近和在非本征基础结构之下。在本征基础结构附近形成发射极结构。外部收集器结构形成在本征收集器结构附近。多个触点通过层间电介质层与外部基极结构，外部基极结构和发射极结构形成。

6. 发明申请

US20050101038A1 Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy 有权
标题翻译：使用自对准外延的异质结双极晶体管的方法和装置
公开(公告)号：US20050101038A1
公开(公告)日：2005-05-12
申请号：US10703297
申请日：2003-11-06
申请人： Purakh Verma , Shao-Fu Chu , Lap Chan , Jian Li , Jia Zheng
发明人： Purakh Verma , Shao-Fu Chu , Lap Chan , Jian Li , Jia Zheng
IPC分类号： H01L21/331 , H01L29/737 , H01L21/00
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个，基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极结构和收集器区域。基底结构和发射极结构优选地形成在相同的处理室中。

7. 发明申请

US20050079678A1 Heterojunction bipolar transistor using reverse emitter window 有权
标题翻译：使用反向发射极窗口的异质结双极晶体管
公开(公告)号：US20050079678A1
公开(公告)日：2005-04-14
申请号：US10683713
申请日：2003-10-09
申请人： Purakh Verma , Shao-Fu Chu , Lap Chan , Jian Li , Jia Zheng
发明人： Purakh Verma , Shao-Fu Chu , Lap Chan , Jian Li , Jia Zheng
IPC分类号： H01L21/331 , H01L29/08 , H01L29/417 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/41708 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an interlevel dielectric layer over the collector region, extrinsic base region and emitter structure, and connections through the interlevel dielectric layer to the base region, the emitter structure, and the collector region. The emitter structure is formed by forming a reverse emitter window over the intrinsic base region, which subsequently is etched to form an emitter window having a multi-layer reverse insulating spacer therein.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，集电极区域上的化合物半导体材料的本征基极区域，非本征基极区域，发射极结构，层间电介质层集电极区域，非本征基极区域和发射极结构以及通过层间介质层到基极区域，发射极结构和集电极区域的连接。通过在本征基极区域上形成反向发射极窗口形成发射极结构，其随后被蚀刻以形成其中具有多层反向绝缘间隔物的发射极窗口。

8. 发明授权

US07060193B2 Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits 失效
标题翻译：在同一电介质区域上形成高k和低k材料的方法及其在混合模式电路中的应用
公开(公告)号：US07060193B2
公开(公告)日：2006-06-13
申请号：US10189876
申请日：2002-07-05
申请人： Pradeep Yelehanka , Sanford Chu , Chit Hwei Ng , Jia Zhen , Purakh Verma
发明人： Pradeep Yelehanka , Sanford Chu , Chit Hwei Ng , Jia Zhen , Purakh Verma
IPC分类号： H01B13/00
CPC分类号： H01L28/55 , H01L21/02109 , H01L21/3127 , H01L21/3144 , H01L21/31625 , H01L21/31629 , H01L27/0617 , H01L27/0629 , H01L27/1203 , H01L2924/0002 , Y10T428/12035 , H01L2924/00
摘要： A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.
摘要翻译：一种提供用于在具有高和低介电常数的半导体材料的一个平面层中形成的新方法。具有选择且优选不相同的介电常数参数的层被依次沉积，散布有蚀刻停止材料层。这些层可以被蚀刻，在那里形成开口，通过这些层可以填充一层选择。

9. 发明申请

US20050196931A1 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US20050196931A1
公开(公告)日：2005-09-08
申请号：US11123748
申请日：2005-05-04
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

10. 发明申请

US20050145953A1 Heterojunction BiCMOS integrated circuits and method therefor 审中-公开
标题翻译：异质结BiCMOS集成电路及其方法
公开(公告)号：US20050145953A1
公开(公告)日：2005-07-07
申请号：US10752454
申请日：2004-01-05
申请人： Lap Chan , Jia Zheng , Purakh Verma , Jian Li , Shao-fu Chu
发明人： Lap Chan , Jia Zheng , Purakh Verma , Jian Li , Shao-fu Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L31/113
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.
摘要翻译：一种制造包括具有栅极结构的CMOS晶体管的BiCMOS集成电路的方法和具有外在基极结构的异质结双极晶体管。提供衬底，并且在衬底上形成多晶硅层。栅极结构和非本征基极结构形成在多晶硅层中。多个触点通过层间介质层形成到CMOS晶体管和异质结双极晶体管。

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