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1. 发明授权

US06265752B1 Method of forming a HVNMOS with an N+ buried layer combined with N well and a structure of the same 有权
标题翻译：用与N阱结合的N +掩埋层形成HVNMOS的方法及其结构
公开(公告)号：US06265752B1
公开(公告)日：2001-07-24
申请号：US09318119
申请日：1999-05-25
申请人： Kou-Chio Liu , Jyh-Min Jiang , Chen-Bau Wu , Ruey-Hsin Liou
发明人： Kou-Chio Liu , Jyh-Min Jiang , Chen-Bau Wu , Ruey-Hsin Liou
IPC分类号： H01L2358
CPC分类号： H01L29/7816 , H01L29/0847 , H01L29/7835
摘要： The device includes a N+ buried layer in a substrate. A P-well is formed in an epitaxial layer on the buried layer. N-wells surround the P-well are also formed in the epitaxial layer. One of the N-well regions acts as a drain in the structure. A plurality of field oxide regions is formed on the N-well or P-well to define the active area of the device. A gate oxide is formed on the surface of the P-well and the N-well served as the drain. A gate is formed on the gate oxide. Drain contact is formed in the N-well for drain. The source region of the device is formed in the P-well adjacent to the drain. An isolation layer is deposited on the gate. The method includes forming a N+ buried layer in a P substrate. A P epitaxial layer is then formed on the surface of the P substrate. The N-well and P-well are respectively formed in the epitaxial layer by ion implantation and thermally diffusion. A plurality of field oxide (FOX) regions are created to define the active area. A gate structure is patterned on the N-well and P-well. A drain contact in the drain (N-well) and a source region in the P-well over the N+ buried layer are formed by conventional manner. An isolation layer is patterned on the gate structure for isolation.
摘要翻译：该器件在衬底中包括N +掩埋层。在掩埋层上的外延层中形成P阱。围绕P阱的N阱也形成在外延层中。其中一个N阱区域作为结构的漏极。在N阱或P阱上形成多个场氧化物区域以限定器件的有效面积。在P阱的表面上形成栅极氧化物，将N阱用作漏极。栅极形成在栅极氧化物上。排水接触形成在N沟用于排水。器件的源极区域形成在与漏极相邻的P阱中。隔离层沉积在栅极上。该方法包括在P衬底中形成N +掩埋层。然后在P基板的表面上形成P外延层。通过离子注入和热扩散分别在外延层中形成N阱和P阱。创建多个场氧化物（FOX）区域以限定有效区域。栅极结构在N阱和P阱上图案化。通过常规方式形成漏极（N阱）中的漏极接触和N +掩埋层上的P阱中的源极区域。在栅极结构上形成隔离层以进行隔离。

2. 发明授权

US06396126B1 High voltage transistor using P+ buried layer 有权
公开(公告)号：US06396126B1
公开(公告)日：2002-05-28
申请号：US09931318
申请日：2001-08-17
申请人： Jun-Lin Tsai , Ruey-Hsin Liu , Jyh-Min Jiang , Jei-Feng Hwang
发明人： Jun-Lin Tsai , Ruey-Hsin Liu , Jyh-Min Jiang , Jei-Feng Hwang
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7392
摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

3. 发明授权

US06590262B2 High voltage ESD protection device with very low snapback voltage 有权
标题翻译：具有极低回跳电压的高压ESD保护器件
公开(公告)号：US06590262B2
公开(公告)日：2003-07-08
申请号：US10082729
申请日：2002-02-26
申请人： Jyh-Min Jiang , Kuo-Chio Liu , Jian-Hsing Lee , Ruey-Hsin Liu
发明人： Jyh-Min Jiang , Kuo-Chio Liu , Jian-Hsing Lee , Ruey-Hsin Liu
IPC分类号： H01L2701
CPC分类号： H01L27/0266 , H01L27/0288 , H01L29/7436 , H01L29/87
摘要： A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+ diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.
摘要翻译：公开了用于保护NMOS高压晶体管的ESD器件的器件布局，其中SCR保护器件和两个NMOS晶体管被集成。两个NMOS晶体管共享一个n型掺杂漏极（ndd）区域，其已经注入了两个n +漏极，一个用于两个晶体管中的每一个，p +扩散分离两个n +漏极。此外，ndd区域已经注入n阱，其从第n +漏极下方的中途延伸到第二n +漏极下方的中间。另外，n阱的深度超过ndd区域的深度。添加的p +扩散与硅晶片的ndd区和p基底一起产生SCR的寄生pnp晶体管。共享的ndd区域与NMOS晶体管的n +源产生SCR两个寄生npn晶体管。 SCR的低触发电压通过n阱，ndd面积，两个漏极之间的p +扩散以及两个寄生npn晶体管并联的组合来实现。

4. 发明授权

US06323074B1 High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain 有权
标题翻译：一种新型的高压ESD保护器件，通过将NMOS +漏极作为p +扩散和n阱加入，具有非常低的回跳电压
公开(公告)号：US06323074B1
公开(公告)日：2001-11-27
申请号：US09557394
申请日：2000-04-24
申请人： Jyh-Min Jiang , Kuo-Chio Liu , Jian-Hsing Lee , Ruey-Hsin Liu
发明人： Jyh-Min Jiang , Kuo-Chio Liu , Jian-Hsing Lee , Ruey-Hsin Liu
IPC分类号： H01L218238
CPC分类号： H01L27/0266 , H01L27/0288 , H01L29/7436 , H01L29/87
摘要： A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.
摘要翻译：公开了用于保护NMOS高压晶体管的ESD器件的器件布局，其中SCR保护器件和两个NMOS晶体管被集成。两个NMOS晶体管共享一个n型掺杂漏极（ndd）区域，其已经注入了两个n +漏极，一个用于两个晶体管中的每一个，p +扩散分离两个n +漏极。此外，ndd区域已经注入n阱，其从第n +漏极下方的中途延伸到第二n +漏极下方的中间。另外，n阱的深度超过ndd区域的深度。添加的p +扩散与硅晶片的ndd区和p基底一起产生SCR的寄生pnp晶体管。共享的ndd区域与NMOS晶体管的n +源产生SCR两个寄生npn晶体管。 SCR的低触发电压通过n阱，ndd面积，两个漏极之间的p +扩散以及两个寄生npn晶体管并联的组合来实现。

5. 发明授权

US06291304B1 Method of fabricating a high voltage transistor using P+ buried layer 有权
标题翻译：使用P +掩埋层制造高压晶体管的方法
公开(公告)号：US06291304B1
公开(公告)日：2001-09-18
申请号：US09396520
申请日：1999-09-15
申请人： Jun-Lin Tsaz , Ruey-Hsin Liu , Jyh-Min Jiang , Jei-Feng Hwang
发明人： Jun-Lin Tsaz , Ruey-Hsin Liu , Jyh-Min Jiang , Jei-Feng Hwang
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7392
摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device)d a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
摘要翻译：公开了一种用于高电压双极晶体管的新设计。代替掩埋子集电极（在NPN器件中将为N +）d使用掩埋的P +层。该P +层的存在导致其本身和双极基底之间的夹断。这样可以实现更高的击穿电压。特别地，该装置不会在作为常规装置的弱点的基极 - 集电极结的底部分解。对该装置的制造方法进行说明。这个新工艺的一个特点是在P +层上生长的N型外延层只是传统器件中其对应厚度的大约一半。该工艺与传统的BiCMOS工艺完全兼容，成本较低。

6. 发明授权

US06242313B1 Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage 有权
标题翻译：使用多晶硅场板来改善高压双极器件击穿电压
公开(公告)号：US06242313B1
公开(公告)日：2001-06-05
申请号：US09389891
申请日：1999-09-03
申请人： Jei-Feng Hwang , Jun-Lin Tsai , Ruey-Hsin Liou , Jyh-Min Jiang
发明人： Jei-Feng Hwang , Jun-Lin Tsai , Ruey-Hsin Liou , Jyh-Min Jiang
IPC分类号： H01L21331
CPC分类号： H01L29/404 , H01L21/765 , H01L21/8249 , H01L29/66272
摘要： A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates,. placed on field oxide regions, in an area of an N well region in which the field oxide regions are located between subsequent P type, base and N type, collector regions. The use of the polysilicon field plates results in an increase in collector—emitter breakdown voltage, as a result of a reduction in the electric field at the surface underlying the polysilicon field plates. The ability to increase collector —emitter breakdowns, via use of only polysilicon field plates, allows the use of higher N well dopant concentrations, thus resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated with the lower N well dopant concentrations, where the lower N well dopant concentration is needed to achieve the desired, increased collector emitter breakdowns.
摘要翻译：已经开发了用于制造具有同时形成的CMOS器件的共享多个工艺步骤的掩埋层夹持集电极双极（BPCB）器件的方法。 BPCB器件制造序列的特点是使用多晶硅场板。放置在场氧化物区域中，其中场氧化物区域位于其间的P型，基极和N型集电极区域的N阱区域的区域中。多晶硅场板的使用导致集电极 - 发射极击穿电压的增加，这是由于多晶硅场板下面的电场的电场减少的结果。通过仅使用多晶硅场板来增加集电极 - 发射体击穿的能力允许使用更高的N阱掺杂剂浓度，从而导致BPCB器件的频率响应（Ft）增加，与使用较低的N阱掺杂剂浓度，其中需要较低的N阱掺杂剂浓度以实现期望的增加的集电极发射极击穿。

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